diff options
author | Martin Roth <martin.roth@se-eng.com> | 2014-07-28 14:22:32 -0600 |
---|---|---|
committer | Martin Roth <gaumless@gmail.com> | 2014-08-11 19:01:25 +0200 |
commit | e6df041b8bf8e37debc0d6a871080b64eea7a372 (patch) | |
tree | 3b97b176f7f9fc15a82d901274bac7d0b0130855 /src/mainboard/intel/minnowmax/dsdt.asl | |
parent | 83da50173ce0547320f029bf3ff46df62c084aac (diff) |
mainboard/intel/minnowmax: Add MinnowMax mainboard
MinnowMax board using Intel's Bay Trail FSP
Working:
- Booting from SATA / USB / (USB3 with latest SeaBIOS)
Not working:
- Boot from SD
- S3 Suspend / Resume
***** To configure the FSP *****
Download the Bay Trail FSP and the binary config tool:
Modify the standard Bay Trail FSP:
run the bct tool with the command line options:
bct --bin <Bay Trail FSP Binary> \
--absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \
--bout <path to save the updated FSP to>
Here are the required changes for modifying the FSP manually:
Enable Memory Down: Enabled
DRAM Speed: 1066 MHz
DIMM_DWidth: x16
DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max)
tCL: 7
tRP_tRCD: 7
tWR: 8
tRRD: 6
tRTP: 4
tFAW: 27
Other FSP values can remain the same.
***** To configure the vbios *****
The vbios is in the Bay Trail FSP package.
Download Intel's "Binary Modification Program" (BMP)
Use it to disable all ports except HDMI on port B.
Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6429
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax/dsdt.asl')
-rw-r--r-- | src/mainboard/intel/minnowmax/dsdt.asl | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000000..cb2a4da3e1 --- /dev/null +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/fsp_baytrail/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> + + #include <soc/intel/fsp_baytrail/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} |