diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2017-02-15 16:13:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-22 23:22:13 +0100 |
| commit | 6530b6d30dd5197ea855c608cecbcdcea8df9e32 (patch) | |
| tree | 9268f38efee623b203723ec971b0ecb2b09972f8 /src/mainboard/intel/minnow3/romstage.c | |
| parent | 97f542efc285a4a2d7245f75cd5f871f5f60b890 (diff) | |
intel/minnow3: Implement and configure GPIO tables
Copy GPIO table implementation from the google/reef board except
with board variant features removed. Also exlcude CrOS GPIO functions.
Remove previous romstage GPIO implementation in brd_gpio.h and romstage.c.
Configure GPIO settings for MinnowBoard 3.
Change-Id: Id2817dcf2f8f196ecd13c810f7f0010a115db566
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18375
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/minnow3/romstage.c')
| -rw-r--r-- | src/mainboard/intel/minnow3/romstage.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c index 04cdad4a57..451e7b4739 100644 --- a/src/mainboard/intel/minnow3/romstage.c +++ b/src/mainboard/intel/minnow3/romstage.c @@ -17,7 +17,6 @@ #include <soc/romstage.h> #include <fsp/api.h> #include <FspmUpd.h> -#include "brd_gpio.h" static const uint8_t Ch0_Bit_swizzling[] = { 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, @@ -46,9 +45,6 @@ static const uint8_t Ch3_Bit_swizzling[] = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* setup early gpio before memory */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; memupd->FspmConfig.Profile = 0xB; |