diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2017-03-23 16:23:47 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-04-07 21:43:06 +0200 |
| commit | 44ff10eaa6f480067b080138ced567122cb2a000 (patch) | |
| tree | 1eab48f38eb38f33f05a19380515ff6607369e4d /src/mainboard/intel/minnow3/minnow3.fmd | |
| parent | 9931f66581f18adcbb2f1efd5cec7119e50a0291 (diff) | |
intel/minnow3: Clean up Kconfig, devicetree and FMAP
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/minnow3/minnow3.fmd')
| -rw-r--r-- | src/mainboard/intel/minnow3/minnow3.fmd | 47 |
1 files changed, 10 insertions, 37 deletions
diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd index 07820470e2..d51b5ee095 100644 --- a/src/mainboard/intel/minnow3/minnow3.fmd +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -1,40 +1,13 @@ FLASH 16M { - WP_RO@0x0 0x480000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x27f000 - RO_VPD@0x280000 0x4000 - RO_SECTION@0x284000 0x1fc000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 - } + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x300000 + FMAP@0x301000 0x800 + COREBOOT(CBFS)@0x301800 0x3dc800 + UNIFIED_MRC_CACHE@0x6de000 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 } - MISC_RW@0x480000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 + DEVICE_EXTENSION@0x6ff000 0x100000 + UNUSED_HOLE@0x7ff000 0x1000 } |