diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2017-02-06 16:07:27 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-02-22 23:21:00 +0100 |
| commit | 35f03d902700e5a9d99a561516588169598b0f07 (patch) | |
| tree | dc1f0e68e74304c4384e33e43fe59d6293888389 /src/mainboard/intel/minnow3/minnow3.fmd | |
| parent | b89b2c50c591bfe308094e35ae45e32df0cb35e2 (diff) | |
mainboard/intel: Add MinnowBoard 3
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/minnow3/minnow3.fmd')
| -rw-r--r-- | src/mainboard/intel/minnow3/minnow3.fmd | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd new file mode 100644 index 0000000000..07820470e2 --- /dev/null +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x480000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x27f000 + RO_VPD@0x280000 0x4000 + RO_SECTION@0x284000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x480000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} |