diff options
| author | Martin Roth <martinroth@google.com> | 2015-12-03 14:02:16 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2015-12-08 00:01:26 +0100 |
| commit | b790fe944d7533b65b37885e0aae43d9826e2086 (patch) | |
| tree | b29901f789c7a1801d24c39b9ddbf6c35c217e03 /src/mainboard/intel/littleplains/Kconfig | |
| parent | b9de78beb67fdf5057e01af7aae198eaacb76d14 (diff) | |
intel/littleplains: Update with recent changes to mohonpeak
- Change SEABIOS_MALLOC_UPPERMEMORY to using PAYLOAD_CONFIGFILE.
- Add saved seabios .config with CONFIG_MALLOC_UPPERMEMORY unset.
- Remove fixed microcode location.
Change-Id: I8b723edf6d6b5542f118e9e0e1aee8104d9cde86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12635
Tested-by: build bot (Jenkins)
Reviewed-by: David Guckian <david.guckian@intel.com>
Diffstat (limited to 'src/mainboard/intel/littleplains/Kconfig')
| -rw-r--r-- | src/mainboard/intel/littleplains/Kconfig | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig index 2fc5cb1934..bde944c4b5 100644 --- a/src/mainboard/intel/littleplains/Kconfig +++ b/src/mainboard/intel/littleplains/Kconfig @@ -58,16 +58,12 @@ config UART_FOR_CONSOLE help The Little Plains board uses COM2 (2f8) for the serial console. -config SEABIOS_MALLOC_UPPERMEMORY - bool - default n +config PAYLOAD_CONFIGFILE + string + default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" help The Avoton/Rangeley chip does not allow devices to write into the 0xe000 segment. This means that USB/SATA devices will not work in SeaBIOS unless we put the SeaBIOS buffer area down in the 0x9000 segment. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xfff60040 - endif # BOARD_INTEL_LITTLEPLAINS |