diff options
| author | Andrey Petrov <andrey.petrov@intel.com> | 2017-02-23 14:10:11 -0800 |
|---|---|---|
| committer | Andrey Petrov <andrey.petrov@intel.com> | 2017-02-25 09:00:50 +0100 |
| commit | 6a489237d5686828f26d7e452824374df7fb5708 (patch) | |
| tree | ca24b0c87fd7c18869cf4d1299e835b35bba998b /src/mainboard/intel/leafhill/leafhill.fmd | |
| parent | 37e30aa624e959bcc5b3a3a2ed1d1337c32afff4 (diff) | |
mainboard/intel/leafhill: Clean up
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18479
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/leafhill/leafhill.fmd')
| -rw-r--r-- | src/mainboard/intel/leafhill/leafhill.fmd | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/src/mainboard/intel/leafhill/leafhill.fmd b/src/mainboard/intel/leafhill/leafhill.fmd deleted file mode 100644 index 3da8467431..0000000000 --- a/src/mainboard/intel/leafhill/leafhill.fmd +++ /dev/null @@ -1,40 +0,0 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - COREBOOT(CBFS)@0x1000 0x1bb000 - RO_UNUSED@0x1bc000 0x40000 - } - } - MISC_RW@0x400000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 -} |