mainboard/intel: add leafhill board directory

This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.

The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.

Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18038
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/mainboard/intel/leafhill/ec.c b/src/mainboard/intel/leafhill/ec.c
new file mode 100644
index 0000000000..646216b8e3
--- /dev/null
+++ b/src/mainboard/intel/leafhill/ec.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <rules.h>
+#include <soc/lpc.h>
+#include <variant/ec.h>
+
+static void ramstage_ec_init(void)
+{
+	printk(BIOS_ERR, "mainboard: EC init\n");
+
+	if (acpi_is_wakeup_s3()) {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S3_WAKE_EVENTS);
+
+		/* Disable SMI and wake events */
+		google_chromeec_set_smi_mask(0);
+
+		/* Clear pending events */
+		while (google_chromeec_get_event() != 0)
+			;
+
+		/* Restore SCI event mask */
+		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+	} else {
+		google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+					   MAINBOARD_EC_S5_WAKE_EVENTS);
+	}
+
+	/* Clear wake event mask */
+	google_chromeec_set_wake_mask(0);
+}
+
+static void bootblock_ec_init(void)
+{
+	uint16_t ec_ioport_base;
+	size_t ec_ioport_size;
+
+	/*
+	 * Set up LPC decoding for the ChromeEC I/O port ranges:
+	 * - Ports 62/66, 60/64, and 200->208
+	 * - ChromeEC specific communication I/O ports.
+	 */
+	lpc_enable_fixed_io_ranges(IOE_EC_62_66 | IOE_KBC_60_64 | IOE_LGE_200);
+	google_chromeec_ioport_range(&ec_ioport_base, &ec_ioport_size);
+	lpc_open_pmio_window(ec_ioport_base, ec_ioport_size);
+}
+
+void mainboard_ec_init(void)
+{
+	if (ENV_RAMSTAGE)
+		ramstage_ec_init();
+	else if (ENV_BOOTBLOCK)
+		bootblock_ec_init();
+}