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| author | Yuchi Chen <yuchi.chen@intel.com> | 2024-09-09 09:53:38 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-09 10:21:25 +0000 |
| commit | f8d4283e78d2df2d63ba8994395b2fc0ee2c84bc (patch) | |
| tree | 759b9df8cbf1427f914920413762bf072448bc57 /src/mainboard/intel/leafhill/dsdt.asl | |
| parent | 60771bfdb102be639b7f074299c5778a8d9b24b9 (diff) | |
arch/x86: Define macros for hard-coded HPET registers
HPET General Capabilities and ID Register at offset 0x0 and Timer 0
Configuration and Capability Register at offset 0x100 are used to
determine the generation of HPET ACPI tables. This patch adds
macro definitions for these registers and fields. Definitions are
from IA-PC HPET (High Precision Event Timers) Specification Revision
1.0a.
Change-Id: I31413afcbfc42307e3ad3f99d75f33f87092d7aa
Signed-off-by: Yuchi Chen <yuchi.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84252
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/leafhill/dsdt.asl')
0 files changed, 0 insertions, 0 deletions