diff options
| author | Brenton Dong <brenton.m.dong@intel.com> | 2017-01-04 16:39:43 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-01-24 18:12:47 +0100 |
| commit | dcc0aa84fa20eaf8feefb21d1662d4716c64ad98 (patch) | |
| tree | 47c981a0978a89335dbaaeab752046c91db6e7b1 /src/mainboard/intel/leafhill/chromeos.fmd | |
| parent | d37fa8d84dc368aa02fa28134f2b7a38d2e3cdf9 (diff) | |
mainboard/intel/leafhill: initial leafhill board changes
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18039
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel/leafhill/chromeos.fmd')
| -rw-r--r-- | src/mainboard/intel/leafhill/chromeos.fmd | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/src/mainboard/intel/leafhill/chromeos.fmd b/src/mainboard/intel/leafhill/chromeos.fmd deleted file mode 100644 index 3c289a1fd4..0000000000 --- a/src/mainboard/intel/leafhill/chromeos.fmd +++ /dev/null @@ -1,53 +0,0 @@ -FLASH 16M { - WP_RO@0x0 0x400000 { - SI_DESC@0x0 0x1000 - IFWI@0x1000 0x1ff000 - RO_VPD@0x200000 0x4000 - RO_SECTION@0x204000 0x1fc000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - COREBOOT(CBFS)@0x1000 0x17b000 - GBB@0x17c000 0x40000 - RO_UNUSED@0x1bc000 0x40000 - } - } - MISC_RW@0x400000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x21000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 - RW_VAR_MRC_CACHE@0x20000 0x1000 - } - RW_ELOG@0x21000 0x3000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x28000 0x2000 - RW_NVRAM@0x2a000 0x6000 - } - RW_SECTION_A@0x430000 0x480000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x46ffc0 - RW_FWID_A@0x47ffc0 0x40 - } - RW_SECTION_B@0x8b0000 0x480000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x46ffc0 - RW_FWID_B@0x47ffc0 0x40 - } - RW_LEGACY(CBFS)@0xd30000 0x200000 - BIOS_UNUSABLE@0xf30000 0x4f000 - DEVICE_EXTENSION@0xf7f000 0x80000 - # Currently, it is required that the BIOS region be a multiple of 8KiB. - # This is required so that the recovery mechanism can find SIGN_CSE - # region aligned to 4K at the center of BIOS region. Since the - # descriptor at the beginning uses 4K and BIOS starts at an offset of - # 4K, a hole of 4K is created towards the end of the flash to compensate - # for the size requirement of BIOS region. - # FIT tool thus creates descriptor with following regions: - # Descriptor --> 0 to 4K - # BIOS --> 4K to 0xf7f000 - # Device ext --> 0xf7f000 to 0xfff000 - UNUSED_HOLE@0xfff000 0x1000 -} |