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authorRohit Ainapure <rohit.m.ainapure@intel.com>2015-12-17 13:52:53 -0800
committerPatrick Georgi <pgeorgi@google.com>2016-01-18 12:17:39 +0100
commit244cf2ecda6e7fd0c25ed4bfee7dea6914e42936 (patch)
tree4242c25fc90c43c63306ee83dfe1f093c1844d88 /src/mainboard/intel/kunimitsu
parenta5244c34b0cc61ea61e735fe93bf31bb74daffbe (diff)
intel/kunimitsu: Set BOOT_BEEP gpio to a default lo
The BOOT_BEEP gpio is used to activate the buffer which isolates the I2S signals from PCH while doing a beep from depthcharge. It needs to be lo to deactivate the buffer for audio playback from OS. BUG=chrome-os-partner:47124 BRANCH=None TEST=boot depthcharge & test beep with devbeep. Boot OS and test audio playback. Change-Id: I047513f6cbe9590820dfe3c369161a157864be97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6 Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1 Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/319220 Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com> Original-Tested-by: Michael Rang <michael.rang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/12988 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/kunimitsu')
-rwxr-xr-xsrc/mainboard/intel/kunimitsu/gpio.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h
index 58b1948445..911dc22365 100755
--- a/src/mainboard/intel/kunimitsu/gpio.h
+++ b/src/mainboard/intel/kunimitsu/gpio.h
@@ -204,7 +204,7 @@ static const struct pad_config gpio_table[] = {
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
-/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 1, DEEP),
+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),