diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-29 11:37:56 -0700 |
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committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-17 20:19:53 +0200 |
commit | c42104189bfe3a192c5f1e4b761d7789abee95b3 (patch) | |
tree | 6c59fc55c95d8306f0622fdad720816c11db6dfb /src/mainboard/intel/kunimitsu/thermal.h | |
parent | 01464a69b8ceaee0e145fcbe61a99e0a077a2332 (diff) |
mainboard/intel: Add Skylake based Kunimitsu board
Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db
This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu
Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/thermal.h')
-rw-r--r-- | src/mainboard/intel/kunimitsu/thermal.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/thermal.h b/src/mainboard/intel/kunimitsu/thermal.h new file mode 100644 index 0000000000..23806c0dfb --- /dev/null +++ b/src/mainboard/intel/kunimitsu/thermal.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _MAINBOARD_THERMAL_H_ +#define _MAINBOARD_THERMAL_H_ + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +/* Tj_max can be read by MSR 0x1A2, BITS[23:16] */ +#define MAX_TEMPERATURE 100 + +#endif /* _MAINBOARD_THERMAL_H_ */ |