diff options
| author | Rizwan Qureshi <rizwan.qureshi@intel.com> | 2016-08-24 20:50:54 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 01:15:27 +0200 |
| commit | 5ff7390fcd74fe1cd94d2507cf7c04b1c1eff620 (patch) | |
| tree | 88ed9f3dc2f5f00aca84af5773debfabd3166120 /src/mainboard/intel/kunimitsu/romstage.c | |
| parent | 5bf42c6c23b462d9292e6854d3f334cf17e42825 (diff) | |
kunimitsu: Add FSP 2.0 support in romstage
Populate mainboard related Memory Init Params i.e, SPD
Rcomp values, DQ and DQs values.
Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16316
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/romstage.c')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/romstage.c | 11 |
1 files changed, 1 insertions, 10 deletions
diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index 84c2b6f534..29ffb61f5c 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -25,16 +25,7 @@ void mainboard_romstage_entry(struct romstage_params *params) { - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - - params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios, - ARRAY_SIZE(spd_gpios)); + params->pei_data->mem_cfg_id = get_spd_index(); /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data); |