mainboard/intel: Add Skylake based Kunimitsu board

Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db

This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.

BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu

Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 23 insertions, 0 deletions

diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c
new file mode 100644
index 0000000000..f9b2764933
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/ramstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "gpio.h"
+#include <soc/ramstage.h>
+
+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
+{
+	/*update gpio table*/
+	params->GpioTablePtr = (UINT32 *)GpioTableKunimitsu;
+}