diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-04-30 12:07:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-03 12:21:17 +0000 |
| commit | ffb5811b325c86ee47d283d694a11ef0860706bb (patch) | |
| tree | 084d5ba4f526372f07af375cbb451bc07a74d387 /src/mainboard/intel/kunimitsu/mainboard.c | |
| parent | e585f5b5cc29b006c551c746fb0bfb5fc69ec358 (diff) | |
soc/intel/jasperlake: Update C-States info
- Update C-States max latency values
- Remove MSR programming for C-States latency
BRANCH=None
TEST=Boot to OS and check CState Latenecy
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048
Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/mainboard.c')
0 files changed, 0 insertions, 0 deletions