diff options
| author | Wenkai Du <wenkai.du@intel.com> | 2015-08-24 10:31:30 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-08-29 07:32:13 +0000 |
| commit | 3b169252ea7c8f16a955890964b30eae19547dd6 (patch) | |
| tree | 80686c69c8a1f5e83bade544d67d852267b0b986 /src/mainboard/intel/kunimitsu/gpio.h | |
| parent | 1105fad6eaae6e4cfb599cffeaca576084719ce8 (diff) | |
intel/kunimitsu: fix SCI handling
Ported below patch from glados to kunimitsu:
glados: Abstract board GPIO configuration in gpio.h
Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Originally-signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Originally-reviewed-on: https://chromium-review.googlesource.com/293942
BUG=chrome-os-partner:40828
BRANCH=none
TEST=Verify that acpi interrupts are incrementing on kunimitsu.
Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad
Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295048
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11432
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/gpio.h')
| -rwxr-xr-x[-rw-r--r--] | src/mainboard/intel/kunimitsu/gpio.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index f1166c8539..0ab36f11ce 100644..100755 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -21,8 +21,21 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include <soc/gpe.h> #include <soc/gpio.h> +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), @@ -198,3 +211,5 @@ static const struct pad_config early_gpio_table[] = { }; #endif + +#endif |