diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-29 11:37:56 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-17 20:19:53 +0200 |
| commit | c42104189bfe3a192c5f1e4b761d7789abee95b3 (patch) | |
| tree | 6c59fc55c95d8306f0622fdad720816c11db6dfb /src/mainboard/intel/kunimitsu/ec.h | |
| parent | 01464a69b8ceaee0e145fcbe61a99e0a077a2332 (diff) | |
mainboard/intel: Add Skylake based Kunimitsu board
Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db
This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu
Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/ec.h')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/ec.h | 70 |
1 files changed, 70 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h new file mode 100644 index 0000000000..9da9d9f0b2 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <ec/google/chromeec/ec_commands.h> + +/* GPP_E16 is EC_SCI_L */ +#define EC_SCI_GPI 16 /* TODO: Update this */ +/* GPP_E15 is EC_SMI_L */ +#define EC_SMI_GPI 15 /* TODO: Update this */ + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +#ifndef __ACPI__ +extern void mainboard_ec_init(void); +#endif + +#endif |