mainboard/intel: Add Skylake based Kunimitsu board

Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db

This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.

BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu

Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 134 insertions, 0 deletions

diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
new file mode 100644
index 0000000000..f1530829bc
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -0,0 +1,134 @@
+chip soc/intel/skylake
+
+	# SerialIO device modes
+	register "SerialIoDevMode" = "{ \
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C2]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C3]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci, \
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci, \
+		[PchSerialIoIndexSpi0]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexSpi1]  = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart0] = PchSerialIoPci, \
+		[PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+		[PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \
+	}"
+
+	register "pirqa_routing" = "0x8b"
+	register "pirqb_routing" = "0x8a"
+	register "pirqc_routing" = "0x8b"
+	register "pirqd_routing" = "0x8b"
+	register "pirqe_routing" = "0x80"
+	register "pirqf_routing" = "0x80"
+	register "pirqg_routing" = "0x80"
+	register "pirqh_routing" = "0x80"
+
+	# EC range is 0x800-0x9ff
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x00fc0901"
+
+	# EC_SMI
+	register "ec_smi_gpio" = "34"
+	register "alt_gp_smi_en" = "0x0400"
+	register "gpe0_en_1" = "0x00000000"
+
+	# EC_SCI is GPIO36
+	register "gpe0_en_2" = "0x00000010"
+	register "gpe0_en_3" = "0x00000000"
+	register "gpe0_en_4" = "0x00000000"
+
+	# Memory related
+	register "IedSize" = "0x0"
+	register "ProbelessTrace" = "0"
+
+	# Lan
+	register "EnableLan" = "0"
+
+	# SATA related
+	register "EnableSata" = "0"
+	register "SataSalpSupport" = "0"
+	register "SataMode" = "0"
+	register "SataPortsEnable[0]" = "0"
+	register "SsicPortEnable" = "0"
+
+	# Audio related
+	register "EnableAzalia" = "1"
+	register "EnableTraceHub" = "0"
+	register "DspEnable" = "1"
+
+	# I/O Buffer Ownership:
+	# 0: HD-A Link
+	# 1 Shared, HD-A Link and I2S Port
+	# 3: I2S Ports
+	register "IoBufferOwnership" = "3"
+
+	# SMBUS
+	register "SmbusEnable" = "1"
+
+	# Camera
+	register "Cio2Enable" = "0"
+
+	# eMMC
+	register "ScsEmmcEnabled" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+	register "ScsSdCardEnabled" = "2"
+
+	# Integrated Sensor
+	register "IshEnable" = "0"
+
+	# XDCI controller
+	register "XdciEnable" = "0"
+
+		device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+					# Refered from SKL EDS Vol 1 : Page No: 31-32
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 14.0 on  end # USB 3.0 xHCI Controller
+		device pci 14.1 off end # USB Device Controller (OTG)
+		device pci 14.2 on  end # Thermal Subsystem
+		device pci 15.0 on  end # I2C Controller #0
+		device pci 15.1 on  end # I2C Controller #1
+		device pci 15.2 on  end # I2C Controller #2
+		device pci 15.3 on  end # I2C Controller #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE Redirection (IDE-R)
+		device pci 16.3 off end # Management Engine Keyboard and Text (KT) Redirection
+		device pci 16.4 off end # Management Engine Intel MEI #3
+		device pci 17.0 off end # SATA Controller
+		device pci 19.0 on  end # UART Controller #2
+		device pci 19.1 on  end # I2C Controller #5
+		device pci 19.2 on  end # I2C Controller #4
+		device pci 1c.0 off end # PCI Express Port 1
+		device pci 1c.1 off end # PCI Express Port 2
+		device pci 1c.2 off end # PCI Express Port 3
+		device pci 1c.3 off end # PCI Express Port 4
+		device pci 1c.4 off end # PCI Express Port 5
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 on  end # UART #1
+		device pci 1e.2 on  end # SPI #0
+		device pci 1e.4 on  end # eMMC
+		device pci 1e.5 off end # SDIO
+		device pci 1e.6 on  end # SDCard
+		device pci 1f.0 on
+			chip ec/google/chromeec
+				device pnp 0c09.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.3 on  end # Intel High Definition Audio (Intel HD Audio) (Audio, Voice, Speech)
+		device pci 1f.4 off end # SMBus Controller
+		device pci 1f.5 on  end # SPI
+		device pci 1f.6 off end # GbE Controller
+	end
+end