diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2015-09-04 10:41:02 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-10 09:52:06 +0000 |
| commit | 74b964ec4ace463d0b221a369a754bc86776e594 (patch) | |
| tree | 3a5bc109379703d7282a3bb33f84eb7a0904f76f /src/mainboard/intel/kunimitsu/devicetree.cb | |
| parent | 963bfa7a0f36d25b22ff221ddc3f1a537bb655a2 (diff) | |
kunimitsu: Clean up mainboard code to match glados
Clean up the intel/kunimitsu mainboard code to match the code
and cleanups in glados. Many of these are trivial changes that
do not impact things in a meaningful way but will make it easier
to diff the code and keep the mainboards in sync.
- use relative path for mainboard includes to make porting easier
- fix trivial style issues to match glados so diffs are clean
- pull GPIO configuration into gpio.h and use from there
- remove thermal.h as it is not used on this board
- make info message BIOS_INFO instead of BIOS_ERR
- add support for SPD manufacturer and part number in SMBIOS
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297752
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index f1480f3d7f..3d6908670a 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable DPTF + register "dptf_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" |