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author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2016-11-05 18:47:51 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2016-11-17 23:08:59 +0100 |
commit | f8a274acf53217129460b5a487396761c174bd54 (patch) | |
tree | 8a83fcef0e7baa711d1ec56adece54dff24a8ad4 /src/mainboard/intel/kunimitsu/chromeos.c | |
parent | 5a043fe08d84490356888d236ee7d190aa195217 (diff) |
rtc: Force negative edge on SET after battery replacement
After the RTC coin cell has been replaced, the Update Cycle Inhibit
bit must see at least one low transition to ensure the RTC counts.
The reset value for this bit is undefined. Examples have been observed
where batteries are installed on a manufacturing line, the bit's state
comes up low, but the RTC does not count.
Change-Id: I05f61efdf941297fa9ec90136124b0c8fe0639c6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/intel/kunimitsu/chromeos.c')
0 files changed, 0 insertions, 0 deletions