mainboard/intel: Add Skylake based Kunimitsu board

Initial files to support the Kunimitsu board.
Matches chromium tree at 927026db

This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.

BRANCH=none
BUG=None
TEST=Build and run ChromeOS on kunimitsu

Change-Id: I1017a66bc811af51a0921e864b589ce2cb618082
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

4 files changed, 216 insertions, 0 deletions

diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
new file mode 100644
index 0000000000..ab1d833c96
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Name (OIPG, Package() {
+	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button
+	Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect
+})
diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl
new file mode 100644
index 0000000000..9ef255320e
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <mainboard/intel/kunimitsu/ec.h>
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
new file mode 100644
index 0000000000..ef119541a5
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl
@@ -0,0 +1,137 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define KUNIMITSU_TRACKPAD_IRQ		0x33
+#define KUNIMITSU_TOUCH_IRQ		0x1f
+
+#define BOARD_TRACKPAD_NAME		"trackpad"
+#define BOARD_TRACKPAD_IRQ		KUNIMITSU_TRACKPAD_IRQ
+#define BOARD_TRACKPAD_I2C_BUS		1
+#define BOARD_TRACKPAD_I2C_ADDR	0x15
+
+#define BOARD_TOUCHSCREEN_NAME		"touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ		KUNIMITSU_TOUCH_IRQ
+#define BOARD_TOUCHSCREEN_I2C_BUS	0
+#define BOARD_TOUCHSCREEN_I2C_ADDR	0x4b
+
+Scope (\_SB)
+{
+	Device (LID0)
+	{
+		Name (_HID, EisaId("PNP0C0D"))
+		Method (_LID, 0)
+		{
+			Return (\_SB.PCI0.LPCB.EC0.LIDS)
+		}
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+}
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+	#include <drivers/pc80/tpm/acpi/tpm.asl>
+}
+Scope (\_SB.PCI0.I2C0)
+{
+	Device (ATSB)
+	{
+		Name (_HID, "ATML0001")
+		Name (_DDN, "Atmel Touchscreen Bootloader")
+		Name (_UID, 4)
+		Name (_S0W, 4)
+		Name (ISTP, 0) /* TouchScreen */
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				0x27,                     // SlaveAddress
+				ControllerInitiated,      // SlaveMode
+				400000,                   // ConnectionSpeed
+				AddressingMode7Bit,       // AddressingMode
+				"\\_SB.PCI0.I2C0",        // ResourceSource
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 }
+		})
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+	Device (ATSA)
+	{
+		Name (_HID, "ATML0001")
+		Name (_DDN, "Atmel Touchscreen")
+		Name (_UID, 5)
+		Name (_S0W, 4)
+		Name (ISTP, 0) /* TouchScreen */
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress
+				ControllerInitiated,        // SlaveMode
+				400000,                     // ConnectionSpeed
+				AddressingMode7Bit,         // AddressingMode
+				"\\_SB.PCI0.I2C0",          // ResourceSource
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				BOARD_TOUCHSCREEN_IRQ
+			}
+		})
+		Method (_STA, 0, NotSerialized)
+		{
+			Return (0xF)
+		}
+	}
+}
+Scope (\_SB.PCI0.I2C1)
+{
+	Device (ELAN)
+	{
+		Name (_HID, "ELAN0000")
+		Name (_DDN, "Elan Touchpad")
+		Name (_UID, 3)
+		Name (_S0W, 4)
+		Name (ISTP, 1) /* TouchPad */
+		Name (_CRS, ResourceTemplate()
+		{
+			I2cSerialBus (
+				BOARD_TRACKPAD_I2C_ADDR,	/* SlaveAddress */
+				ControllerInitiated,		/* SlaveMode */
+				400000,				/* ConnectionSpeed */
+				AddressingMode7Bit,		/* AddressingMode */
+				"\\_SB.PCI0.I2C1",		/* ResourceSource */
+			)
+			Interrupt (ResourceConsumer, Edge, ActiveLow)
+			{
+				KUNIMITSU_TRACKPAD_IRQ
+			}
+		})
+		Method (_STA)
+		{
+			Return (0xF)
+		}
+	}
+}
diff --git a/src/mainboard/intel/kunimitsu/acpi/superio.asl b/src/mainboard/intel/kunimitsu/acpi/superio.asl
new file mode 100644
index 0000000000..747991e7f5
--- /dev/null
+++ b/src/mainboard/intel/kunimitsu/acpi/superio.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* mainboard configuration */
+#include <mainboard/intel/kunimitsu/ec.h>
+
+#define SIO_EC_MEMMAP_ENABLE     // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE       // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K       // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>