diff options
| author | Naresh G Solanki <naresh.solanki@intel.com> | 2016-11-06 14:05:35 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-11-07 20:53:54 +0100 |
| commit | dd397f0971c140e3a5b80eb0c568384c154a60e6 (patch) | |
| tree | d2565123c1c1947ed5947bb57772ccca1451c22c /src/mainboard/intel/kblrvp | |
| parent | bc6a3890499a7459d0592a872334a09d0514d78b (diff) | |
mainboard/intel/kblrvp: Add Chrome EC switch
Add Chrome EC switch to enable building with/without Chrome EC.
Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17248
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/kblrvp')
| -rw-r--r-- | src/mainboard/intel/kblrvp/acpi/ec.asl | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/acpi/mainboard.asl | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/chromeos.c | 41 |
3 files changed, 30 insertions, 16 deletions
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl index 2203e2f7f0..7d7ff2ffa8 100644 --- a/src/mainboard/intel/kblrvp/acpi/ec.asl +++ b/src/mainboard/intel/kblrvp/acpi/ec.asl @@ -22,6 +22,7 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE - +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> +#endif diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl index 1b8fe431e6..5d2b3071b5 100644 --- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl @@ -16,6 +16,7 @@ #include "../gpio.h" +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) Scope (\_SB) { Device (LID0) @@ -34,6 +35,7 @@ Scope (\_SB) Name (_HID, EisaId ("PNP0C0C")) } } +#endif /* * LPC Trusted Platform Module diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c index a9704daa64..fc1bcd2b9d 100644 --- a/src/mainboard/intel/kblrvp/chromeos.c +++ b/src/mainboard/intel/kblrvp/chromeos.c @@ -40,8 +40,6 @@ void fill_lb_gpios(struct lb_gpios *gpios) {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, - {GPIO_EC_IN_RW, ACTIVE_HIGH, - gpio_get(GPIO_EC_IN_RW), "EC in RW"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } @@ -49,8 +47,12 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - /* Read lid switch state from the EC. */ - return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); + + /* Lid always open */ + return 1; } int get_developer_mode_switch(void) @@ -61,31 +63,40 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - /* Check for dedicated recovery switch first. */ - if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) { + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & + EC_SWITCH_DEDICATED_RECOVERY) return 1; - /* Otherwise check if the EC has posted the keyboard recovery event. */ - return !!(google_chromeec_get_events_b() & - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + /* Otherwise check if the EC has posted the keyboard recovery + * event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + } + + return 0; } int clear_recovery_mode_switch(void) { - /* Clear keyboard recovery event. */ - return google_chromeec_clear_events_b( - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); + + return 0; } int get_write_protect_state(void) { - /* Read PCH_WP GPIO. */ - return gpio_get(GPIO_PCH_WP); + /* No write protect */ + return 0; } static const struct cros_gpio cros_gpios[] = { CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), }; void mainboard_chromeos_acpi_generate(void) |