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authorSubrata Banik <subrata.banik@intel.com>2019-01-14 20:03:56 +0530
committerPatrick Georgi <pgeorgi@google.com>2019-01-16 16:26:56 +0000
commit1ed36f9ce9d52917a04cfbe5c3b353910ca7fd1c (patch)
tree5eaa7e4a415d1af6a6c15b6dd11c0ff76a18a755 /src/mainboard/intel/kblrvp
parentd4a12ec82204b9acf8dc814103e4f2efefecd248 (diff)
mainboard/intel: Update mainboard UART Kconfig
After a96e66a (soc/intel: Clean mess around UART_DEBUG) got merged, all mainboard using intel cannonlake,coffeelake, kabylake, skylake, icelake and whiskeylake get affected. Using INTEL_LPSS_UART_FOR_CONSOLE instead of UART_DEBUG and set default console for each platform. TEST=Intel client and IoT team has verified that LPSS uart is working fine on CNL, WHL and ICL RVPs. Change-Id: I0381a6616f03c74c98f837e3c008459fefd4818c Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/30913 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp')
-rw-r--r--src/mainboard/intel/kblrvp/Kconfig5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index c3a0400b59..3795cce9f1 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_CHROMEOS
select GENERIC_SPD_BIN
select MAINBOARD_HAS_LPC_TPM
+ select INTEL_LPSS_UART_FOR_CONSOLE
config VBOOT
select VBOOT_LID_SWITCH
@@ -84,4 +85,8 @@ config PRERAM_CBMEM_CONSOLE_SIZE
config DIMM_SPD_SIZE
int
default 512 if BOARD_INTEL_KBLRVP8 || BOARD_INTEL_KBLRVP11 #DDR4
+
+config UART_FOR_CONSOLE
+ int
+ default 2
endif