diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-08-17 15:49:58 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-08-25 17:58:08 +0000 |
| commit | c204aaa23b8455457920a56a85b0128f9818f461 (patch) | |
| tree | aab5c43aae02df5f04ccea3d903a04d887012c9d /src/mainboard/intel/kblrvp | |
| parent | bcefbe163f70ef2590be252057d626e788047b16 (diff) | |
soc/intel/skylake: Add LPC and SPI lock down config option
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/kblrvp')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index c1974ad718..0d2bd0f397 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -205,6 +205,9 @@ chip soc/intel/skylake # Enable/Disable VMX feature register "VmxEnable" = "0" + # Lock Down + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index a56345c00d..6f45a46a7d 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -200,6 +200,9 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio_default" = "GPP_G5" + # Lock Down + register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end |