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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 12:54:48 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 12:21:14 +0000
commite16692ed07ec5a2deaf9769f4ecc3d65dd21ce1d (patch)
treea3d4794fb34e6f00d9aee3efc04b1a9173928304 /src/mainboard/intel/kblrvp/variants
parent20245aa622d4224ecd2cdc88438d29f7b5868744 (diff)
mb/**/{devicetree,overridetree}.cb: Indent with tabs
Use tabs instead of eight (sometimes less) spaces. Change-Id: Ic3d61f5210d21d9613fc50b47b90af71f544169a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants')
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb4
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb38
2 files changed, 21 insertions, 21 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index 5cfb10da50..9c9a2e767b 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -7,8 +7,8 @@ chip soc/intel/skylake
register "gen2_dec" = "0x000c0201"
# FSP Configuration
- register "DspEnable" = "1"
- register "IoBufferOwnership" = "0"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "0"
register "HeciEnabled" = "0"
register "PmTimerDisabled" = "1"
register "Cio2Enable" = "1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index e6c5c38d73..26be7dd751 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -117,25 +117,25 @@ chip soc/intel/skylake
register "PcieRpClkSrcNumber[8]" = "1"
# USB 2.0 Enable all ports
- register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
- register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
- register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port
- register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
- register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
- register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
-
- # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
- register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
- register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
- register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
- register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
- register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[0]" = "USB2_PORT_MAX(OC0)" # TYPE-A Port
+ register "usb2_ports[1]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[2]" = "USB2_PORT_MAX(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MAX(OC1)" # Type-A Port
+ register "usb2_ports[5]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[6]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[7]" = "USB2_PORT_MAX(OC2)" # TYPE-A Port
+ register "usb2_ports[8]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[9]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[10]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+ register "usb2_ports[11]" = "USB2_PORT_MAX(OC_SKIP)" # TYPE-A Port
+
+ # USB 3.0 Enable Port 1-4. Port 5 & 6 Disabled
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # TYPE-A Port
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # TYPE-A Port
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # TYPE-A Port
+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPE-A Port
register "SerialIoDevMode" = "{ \
[PchSerialIoIndexI2C0] = PchSerialIoPci, \