diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-23 00:25:18 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-26 11:43:56 +0000 |
| commit | 6c83a71b0a803c922b02b613e927d4c49b944c32 (patch) | |
| tree | 176f163e7fdeaaf1032c853e87ce5571bd921be7 /src/mainboard/intel/kblrvp/variants | |
| parent | c7c8cf2edd713fd578423bc043403ae4f91e2e29 (diff) | |
skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants')
4 files changed, 108 insertions, 100 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index b580e76241..f2e569ddfd 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -46,35 +46,6 @@ chip soc/intel/skylake # USB related register "SsicPortEnable" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ - [1] = USB2_PORT_MID(OC3), /* Touch Pad */ - [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ - [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ - [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ - [5] = USB2_PORT_MID(OC0), /* Front Panel */ - [6] = USB2_PORT_MID(OC0), /* Front Panel */ - [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ - [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ - [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ - [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ - [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ - [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ - [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ - [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ - }" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ @@ -107,6 +78,37 @@ chip soc/intel/skylake }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ + [1] = USB2_PORT_MID(OC3), /* Touch Pad */ + [2] = USB2_PORT_MID(OC_SKIP), /* M.2 BT */ + [3] = USB2_PORT_MID(OC_SKIP), /* Touch Panel */ + [4] = USB2_PORT_MID(OC_SKIP), /* M.2 WWAN */ + [5] = USB2_PORT_MID(OC0), /* Front Panel */ + [6] = USB2_PORT_MID(OC0), /* Front Panel */ + [7] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [8] = USB2_PORT_MID(OC2), /* Stacked conn (lan + usb) */ + [9] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [10] = USB2_PORT_MID(OC1), /* LAN MAGJACK */ + [11] = USB2_PORT_MID(OC_SKIP), /* Finger print sensor */ + [12] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + [13] = USB2_PORT_MID(OC4), /* USB 2 stack conn */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC5), /* OTG */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* M.2 WWAN */ + [2] = USB3_PORT_DEFAULT(OC3), /* Flex */ + [3] = USB3_PORT_DEFAULT(OC_SKIP), /* IVCAM */ + [4] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + [5] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [6] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [7] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [8] = USB3_PORT_DEFAULT(OC2), /* Stack Conn */ + [9] = USB3_PORT_DEFAULT(OC1), /* LAN MAGJACK */ + }" + end device ref sa_thermal off end device ref i2c2 off end device ref i2c3 off end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index b7c4395bd1..81557eb8ff 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -74,26 +74,6 @@ chip soc/intel/skylake # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ - [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ - [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ - [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ - }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -113,6 +93,28 @@ chip soc/intel/skylake }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC_SKIP), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC1), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + }" + end device ref imgu on end device ref cio on end device ref pcie_rp1 on end # x4 SLOT1 diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index ce4bf4b81b..9e8c8140ac 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -113,28 +113,6 @@ chip soc/intel/skylake # RP 9 uses CLK SRC 1# register "PcieRpClkSrcNumber[8]" = "1" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ - [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ - [4] = USB2_PORT_MAX(OC1), /* Type-A Port */ - [5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ - [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ - [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ - [4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */ - [5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -154,6 +132,30 @@ chip soc/intel/skylake register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ + [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [2] = USB2_PORT_MAX(OC_SKIP), /* Bluetooth */ + [4] = USB2_PORT_MAX(OC1), /* Type-A Port */ + [5] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [6] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [7] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ + [8] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [9] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [10] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + [11] = USB2_PORT_MAX(OC_SKIP), /* TYPE-A Port */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* TYPE-A Port */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [2] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + [3] = USB3_PORT_DEFAULT(OC1), /* TYPE-A Port */ + [4] = USB3_PORT_DEFAULT(OC2), /* TYPE-A Port */ + [5] = USB3_PORT_DEFAULT(OC_SKIP), /* TYPE-A Port */ + }" + end device ref i2c2 off end device ref i2c3 off end device ref sata on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 2291c637fd..8e70c1e971 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -95,35 +95,6 @@ chip soc/intel/skylake register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[16]" = "7" - register "usb2_ports" = "{ - [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ - [1] = USB2_PORT_MAX(OC5), /* Front panel */ - [2] = USB2_PORT_MAX(OC4), /* Back panel */ - [3] = USB2_PORT_MAX(OC4), /* Back panel */ - [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */ - [5] = USB2_PORT_MAX(OC1), /* Back panel */ - [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */ - [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */ - [9] = USB2_PORT_MAX(OC2), /* Front panel */ - [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */ - [12] = USB2_PORT_MAX(OC3), /* Back panel */ - [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ - }" - - register "usb3_ports" = "{ - [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */ - [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */ - [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */ - [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */ - [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ - [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */ - [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ - [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ - [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */ - [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */ - }" register "SsicPortEnable" = "1" # Enable SSIC for WWAN @@ -160,6 +131,37 @@ chip soc/intel/skylake }" device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ + [1] = USB2_PORT_MAX(OC5), /* Front panel */ + [2] = USB2_PORT_MAX(OC4), /* Back panel */ + [3] = USB2_PORT_MAX(OC4), /* Back panel */ + [4] = USB2_PORT_MAX(OC1), /* Back panel-1 */ + [5] = USB2_PORT_MAX(OC1), /* Back panel */ + [6] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + [7] = USB2_PORT_MAX(OC_SKIP), /* Front panel */ + [8] = USB2_PORT_MAX(OC_SKIP), /* M.2 BT */ + [9] = USB2_PORT_MAX(OC2), /* Front panel */ + [10] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + [11] = USB2_PORT_MAX(OC_SKIP), /* Back panel-1 */ + [12] = USB2_PORT_MAX(OC3), /* Back panel */ + [13] = USB2_PORT_MAX(OC_SKIP), /* Back panel */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C Port */ + [1] = USB3_PORT_DEFAULT(OC1), /* Back panel */ + [2] = USB3_PORT_DEFAULT(OC1), /* Back panel */ + [3] = USB3_PORT_DEFAULT(OC0), /* Back panel-2 */ + [4] = USB3_PORT_DEFAULT(OC0), /* Front Panel */ + [5] = USB3_PORT_DEFAULT(OC_SKIP), /* Front Panel */ + [6] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ + [7] = USB3_PORT_DEFAULT(OC2), /* Front Panel */ + [8] = USB3_PORT_DEFAULT(OC3), /* Back panel */ + [9] = USB3_PORT_DEFAULT(OC_SKIP), /* LAN */ + }" + end device ref i2c2 off end device ref i2c3 off end device ref sata on end |