diff options
| author | V Sowmya <v.sowmya@intel.com> | 2017-07-18 12:08:13 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 00:31:31 +0000 |
| commit | 0f307957b419a2099bb128f2cec35a16550e643e (patch) | |
| tree | c601b39f57e61656eab6ae9507de4bfd70e0318d /src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | |
| parent | 58eb6346594c07ee470e94c3b00885d0c734d167 (diff) | |
mainboard/intel/kblrvp: Add MIPI camera support
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index ac99a211ef..c1974ad718 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -37,6 +37,8 @@ chip soc/intel/skylake register "HeciEnabled" = "0" register "SaGv" = "3" register "PmTimerDisabled" = "1" + register "Cio2Enable" = "1" + register "SaImguEnable" = "1" register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" @@ -186,8 +188,8 @@ chip soc/intel/skylake register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ - [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ [PchSerialIoIndexI2C4] = PchSerialIoPci, \ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \ @@ -214,8 +216,8 @@ chip soc/intel/skylake device pci 14.2 on end # Thermal Subsystem device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R |