mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c

1. Update gpio.h to set proper pad config for Kaby Lake RVP3.
2. Set spd index to zero.
3. Remove nhlt specific init.

Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

2 files changed, 5 insertions, 47 deletions

diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
index e04d13c3fb..6199fb5a1a 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.h
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -24,8 +24,8 @@
 #define SPD_LEN			256
 
 #define SPD_DRAM_TYPE		2
-#define  SPD_DRAM_DDR3		0x0b
-#define  SPD_DRAM_LPDDR3	0xf1
+#define  SPD_DRAM_DDR3		0x0B
+#define  SPD_DRAM_LPDDR3	0x0F
 #define SPD_DENSITY_BANKS	4
 #define SPD_ADDRESSING		5
 #define SPD_ORGANIZATION	7
@@ -34,26 +34,8 @@
 #define  SPD_PART_LEN		18
 #define SPD_MANU_OFF		148
 
-#define HYNIX_SINGLE_CHAN	0x1
-#define SAMSUNG_SINGLE_CHAN	0x4
-#define MIC_SINGLE_CHAN		0x5
-
-/* PCH_MEM_CFG[3:0] */
-#define MAX_MEMORY_CONFIG	0x10
 #define RCOMP_TARGET_PARAMS	0x5
-#define K4E6E304EE_MEM_ID	0x3
 
-static inline int get_spd_index(void)
-{
-	/* PCH_MEM_CFG[3:0] */
-	gpio_t spd_gpios[] = {
-		GPIO_MEM_CONFIG_0,
-		GPIO_MEM_CONFIG_1,
-		GPIO_MEM_CONFIG_2,
-		GPIO_MEM_CONFIG_3,
-	};
-	return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
-}
 void mainboard_fill_dq_map_data(void *dq_map_ptr);
 void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
 void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index fc0581cb24..68bdb48b6b 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -52,25 +52,11 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
 
 void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
 {
-	int mem_cfg_id;
-
-	mem_cfg_id = get_spd_index();
 	/* Rcomp target */
 	static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
 		100, 40, 40, 23, 40 };
 
-	/* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */
-	static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {
-		100, 40, 40, 21, 40 };
-
-
-	if (mem_cfg_id == K4E6E304EE_MEM_ID) {
-		memcpy(rcomp_strength_ptr, StrengthendRcompTarget,
-			sizeof(StrengthendRcompTarget));
-	} else {
-		memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
-	}
-
+	memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
 }
 
 uintptr_t mainboard_get_spd_data(void)
@@ -79,7 +65,7 @@ uintptr_t mainboard_get_spd_data(void)
 	int spd_index, spd_span;
 	size_t spd_file_len;
 
-	spd_index = get_spd_index();
+	spd_index = 0;
 	printk(BIOS_INFO, "SPD index %d\n", spd_index);
 
 	/* Load SPD data from CBFS */
@@ -104,15 +90,5 @@ uintptr_t mainboard_get_spd_data(void)
 
 int mainboard_has_dual_channel_mem(void)
 {
-	int spd_index;
-
-	spd_index = get_spd_index();
-
-	if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN
-		&& spd_index != MIC_SINGLE_CHAN) {
-		printk(BIOS_INFO,
-			"Dual channel SPD detected writing second channel\n");
-		return 1;
-	}
-	return 0;
+	return 1;
 }