diff options
| author | Karthikeyan Ramasubramanian <kramasub@google.com> | 2020-08-06 22:58:08 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-17 06:37:26 +0000 |
| commit | 8beb5ba230ff30126fcc169a11d1b3291c4fe9dc (patch) | |
| tree | e162e2de8ba0431c843259f1e1f18bc19618c739 /src/mainboard/intel/jasperlake_rvp | |
| parent | 2a66dd2cc2dc821b5724c28eb8df81fa60486e16 (diff) | |
mb/intel/jasperlake_rvp: Re-organize the FMAP layout
More space is required in the COREBOOT CBFS to accommodate some features.
Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has
~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend
the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So
adjust the GBB region accordingly and extend the COREBOOT CBFS.
BUG=b:162159386
TEST=Build the JSLRVP mainboard.
Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7
Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Diffstat (limited to 'src/mainboard/intel/jasperlake_rvp')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 827e4484ca..05f45922e2 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -28,15 +28,15 @@ FLASH@0xff000000 0x1000000 { RW_VPD(PRESERVE)@0x28000 0x2000 RW_NVRAM(PRESERVE)@0x2a000 0x6000 } - RW_LEGACY(CBFS)@0x5d0000 0x100000 - WP_RO@0x6d0000 0x330000 { + RW_LEGACY(CBFS)@0x5d0000 0x30000 + WP_RO@0x600000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x32c000 { + RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 RO_FRID@0x800 0x40 RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x23c000 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 } } } |