mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP

Add memory initialization parameters for Jasper Lake RVP boards
Jasper Lake RVP supports two variants, one with memory LPDDR4
and another with DDR4
Based on board id, mainboard will pass correct memory parameters
to the fsp.

BUG=None
BRANCH=None
TEST=Check compilation for Jasper Lake RVP and check memory training passes.

Change-Id: Idc92363a2148990df16c2068c7986013d015f604
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 30 insertions, 4 deletions

diff --git a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
index b072a9099d..8858e44616 100644
--- a/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/jasperlake_rvp/romstage_fsp_params.c
@@ -1,6 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
+ * Copyright 2020 The coreboot project Authors
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -11,11 +12,36 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
-
-#include <fsp/api.h>
+#include <baseboard/variants.h>
+#include <console/console.h>
+#include <soc/meminit_jsl.h>
 #include <soc/romstage.h>
+#include "board_id.h"
 
-void mainboard_memory_init_params(FSPM_UPD *mupd)
+void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	/* ToDo : Fill FSP-M memory params */
+	static struct spd_info jslrvp_spd_info;
+	uint8_t board_id = get_board_id();
+	const struct mb_cfg *board_cfg = variant_memcfg_config(board_id);
+
+	/* TODO: Read the resistor strap to get number of memory segments */
+	bool half_populated = false;
+
+	/* Check board id and fill correct parameters to upd */
+	if (board_id == jsl_ddr4) {
+		/* Initialize spd information for DDR4 board */
+		jslrvp_spd_info.read_type = READ_SMBUS;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[0] = 0xA0;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[1] = 0xA2;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[2] = 0xA4;
+		jslrvp_spd_info.spd_spec.spd_smbus_address[3] = 0xA6;
+
+	} else if (board_id == jsl_lpddr4) {
+		/* Initialize spd information for LPDDR4 board */
+		jslrvp_spd_info.read_type = READ_SPD_CBFS;
+		jslrvp_spd_info.spd_spec.spd_index = 0x00;
+	}
+
+	/* Initialize variant specific configurations */
+	memcfg_init(&memupd->FspmConfig, board_cfg, &jslrvp_spd_info, half_populated);
 }