mainboard/intel/icelake_rvp: Do initial mainboard commit

Clone entirely from mainboard/intel/cannonlake_rvp
commit id: af89f49b83260a04dece84b34e97560fb85d29ae

List of changes on top off initial cannonlake_rvp clone
 1. Rename "Cannonlake" with "Icelake".
 2. Replace "cannonlake_rvp" with "icelake_rvp".
 3. Rename "cnl" with "icl".
 4. Remove unwanted SPD file, will add correct SPD with mainboard
    patches.
 5. Remove NHLT related implementation.
 6. Remove FSP configs, will add once FSP headers are available.
 7. Removed smihandler.c, will add later if needed.

Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29164
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 689 insertions, 0 deletions

diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000000..9fb63f5f43
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/Makefile.inc
@@ -0,0 +1,3 @@
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c
new file mode 100644
index 0000000000..56604cf6fe
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/gpio.c
@@ -0,0 +1,320 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* GPPC */
+	/* A0  : RCINB_TIME_SYNC_1 */
+	/* A1  : ESPI_IO_0 */
+	/* A2  : ESPI_IO_1 */
+	/* A3  : ESPI_IO_2 */
+	/* A4  : ESPI_IO_3 */
+	/* A5  : ESPI_CSB */
+	/* A6  : SERIRQ */
+	/* A7  : PRIQAB_GSP10_CS1B */
+	PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE),
+	/* A8  : CLKRUNB */
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
+	/* A9  : CLKOUT_LPC_0_ESPI_CLK */
+	/* A10 : CLKOUT_LPC_1 */
+	/* A11 : PMEB_GSP11_CS1B */
+	PAD_CFG_GPI_SCI_LOW(GPP_A11, UP_20K, DEEP, LEVEL),
+	/* A12 : BM_BUSYB_ISH__GP_6 */
+	/* A13 : SUSWARNB_SUSPWRDNACK */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	/* A14 : SUS_STATB_ESPI_RESETB */
+	/* A15 : SUSACKB */
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+	/* A16 : SD_1P8_SEL */
+	PAD_CFG_GPO(GPP_A16, 0, PLTRST),
+	/* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */
+	/* A18 : ISH_GP_0 */
+	PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1),
+	/* A19 : ISH_GP_1 */
+	PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1),
+	/* A20 : aduio codec irq  */
+	PAD_CFG_GPI_APIC_LOW(GPP_A20, NONE, DEEP),
+	/* A21 : ISH_GP_3 */
+	PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1),
+	/* A22 : ISH_GP_4 */
+	PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1),
+	/* A23 : ISH_GP_5 */
+	PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1),
+
+	/* B0  : CORE_VID_0 */
+	/* B1  : CORE_VID_1 */
+	/* B2  : VRALERTB */
+	PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP, LEVEL, NONE),
+	/* B3  : CPU_GP_2 */
+	PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE),
+	/* B4  : CPU_GP_3 */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* B5  : SRCCLKREQB_0 */
+	/* B6  : SRCCLKREQB_1 */
+	/* B7  : SRCCLKREQB_2 */
+	/* B8  : SRCCLKREQB_3 */
+	/* B9  : SRCCLKREQB_4 */
+	/* B10 : SRCCLKREQB_5 */
+	/* B11 : EXT_PWR_GATEB */
+	PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
+	/* B12 : SLP_S0B */
+	/* B13 : PLTRSTB */
+	/* B14 : SPKR */
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+	/* B15 : GSPI0_CS0B */
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	/* B16 : GSPI0_CLK */
+	PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE),
+	/* B17 : GSPI0_MISO */
+	PAD_CFG_GPO(GPP_B17, 1, PLTRST),
+	/* B18 : GSPI0_MOSI */
+	PAD_CFG_GPO(GPP_B18, 1, PLTRST),
+	/* B19 : GSPI1_CS0B */
+	/* B20 : GSPI1_CLK_NFC_CLK */
+	/* B21 : GSPI1_MISO_NFC_CLKREQ */
+	/* B22 : GSP1_MOSI */
+	/* B23 : SML1ALERTB_PCHHOTB */
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
+
+	/* C0  : SMBCLK */
+	/* C1  : SMBDATA */
+	/* C2  : SMBALERTB */
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+	/* C3  : SML0CLK */
+	/* C4  : SML0DATA */
+	/* C5  : SML0ALERTB */
+	PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),
+	/* C6  : SML1CLK */
+	/* C7  : SML1DATA */
+	/* C8  : UART0_RXD */
+	PAD_CFG_GPI_APIC(GPP_C8, UP_20K, DEEP, LEVEL, INVERT),
+	/* C9  : UART0_TXD */
+	PAD_CFG_GPI_SCI_LOW(GPP_C9, UP_20K, PLTRST, EDGE_SINGLE),
+	/* C10 : UART0_RTSB */
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+	/* C11 : UART0_CTSB */
+	PAD_CFG_GPI_SCI_LOW(GPP_C11, UP_20K, DEEP, LEVEL),
+	/* C12 : UART1_RXD_ISH_UART1_RXD */
+	PAD_CFG_GPO(GPP_C12, 1, PLTRST),
+	/* C13 : UART1_RXD_ISH_UART1_TXD */
+	/* C14 : UART1_RXD_ISH_UART1_RTSB */
+	/* C15 : UART1_RXD_ISH_UART1_CTSB */
+	PAD_CFG_GPO(GPP_C15, 1, PLTRST),
+	/* C16 : I2C0_SDA */
+	/* C17 : I2C0_SCL */
+	/* C18 : I2C1_SDA */
+	/* C19 : I2C1_SCL */
+	/* C20 : UART2_RXD */
+	/* C21 : UART2_TXD */
+	/* C22 : UART2_RTSB */
+	/* C23 : UART2_CTSB */
+
+	/* D0  : SPI1_CSB_BK_0 */
+	/* D1  : SPI1_CLK_BK_1 */
+	/* D2  : SPI1_MISO_IO_1_BK_2 */
+	/* D3  : SPI1_MOSI_IO_0_BK_3 */
+	/* D4  : IMGCLKOUT_0_BK_4 */
+	/* D5  : ISH_I2C0_SDA */
+	/* D6  : ISH_I2C0_SCL */
+	/* D7  : ISH_I2C1_SDA */
+	/* D8  : ISH_I2C1_SCL */
+	/* D9  : ISH_SPI_CSB */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+	/* D10 : ISH_SPI_CLK */
+	PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST, EDGE_SINGLE, NONE),
+	/* D11 : ISH_SPI_MISO_GP_BSSB_CLK */
+	PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),
+	/* D12 : ISH_SPI_MOSI_GP_BSSB_DI */
+	/* D13 : ISH_UART0_RXD_SML0BDATA */
+	PAD_CFG_GPO(GPP_D13, 1, DEEP),
+	/* D14 : ISH_UART0_TXD_SML0BCLK */
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	/* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */
+	/* D16 : ISH_UART0_CTSB_SML0BALERTB */
+	PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),
+	/* D17 : DMIC_CLK_1_SNDW3_CLK */
+	PAD_CFG_NF(GPP_D17, UP_20K, DEEP, NF1),
+	/* D18 : DMIC_DATA_1_SNDW3_DATA */
+	PAD_CFG_NF(GPP_D18, UP_20K, DEEP, NF1),
+	/* D19 : DMIC_CLK_0_SNDW4_CLK */
+	PAD_CFG_NF(GPP_D19, UP_20K, DEEP, NF1),
+	/* D20 : DMIC_DATA_0_SNDW4_DATA */
+	PAD_CFG_NF(GPP_D20, UP_20K, DEEP, NF1),
+	/* D21 : SPI1_IO_2 */
+	PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),
+	/* D22 : SPI1_IO_3 */
+	PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),
+	/* D23 : SPP_MCLK */
+	PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+	/* E0  : SATAXPCIE_0_SATAGP_0 */
+#if IS_ENABLED(CONFIG_BOARD_INTEL_ICELAKE_RVPY)
+	PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1),
+#endif
+	/* E1  : SATAXPCIE_1_SATAGP_1 */
+	/* E2  : SATAXPCIE_2_SATAGP_2 */
+	PAD_CFG_GPI(GPP_E2, UP_20K, PLTRST),
+	/* E3  : CPU_GP_0 */
+	PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
+	/* E4  : SATA_DEVSLP_0 */
+	PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),
+	/* E5  : SATA_DEVSLP_1 */
+	/* E6  : SATA_DEVSLP_2 */
+	PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE),
+	/* E7  : CPU_GP_1 */
+	PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE),
+	/* E8  : SATA_LEDB */
+	/* E9  : USB2_OCB_0_GP_BSSB_CLK */
+	/* E10 : USB2_OCB_1_GP_BSSB_DI */
+	/* E11 : USB2_OCB_2 */
+	/* E12 : USB2_OCB_3 */
+	/* E13 : DDSP_HPD_0_DISP_MISC_0 */
+	/* E14 : DDSP_HPD_0_DISP_MISC_1 */
+	/* E15 : DDSP_HPD_0_DISP_MISC_2 */
+	/* E16 : EMMC_EN */
+	PAD_CFG_GPO(GPP_E16, 1, PLTRST),
+	/* E17 : EDP_HPD_DISP_MISC_4 */
+	/* E18 : DDPB_CTRLCLK */
+	/* E19 : DDPB_CTRLDATA */
+	/* E20 : DDPC_CTRLCLK */
+	/* E21 : DDPC_CTRLDATA */
+	/* E22 : DDPD_CTRLCLK */
+	/* E23 : DDPD_CTRLDATA */
+
+	/* F0  : CNV_GNSS_PA_BLANKING */
+	PAD_CFG_GPI(GPP_F0, NONE, PLTRST),
+	/* F1  : CNV_GNSS_FAT */
+	PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP),
+	/* F2  : CNV_GNSS_SYSCK */
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
+	/* F3  : GPP_F_3 */
+	PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
+	/* F4  : CNV_BRI_DT_UART0_RTSB */
+	/* F5  : CNV_BRI_RSP_UART0_RXD */
+	/* F6  : CNV_RGI_DT_UART0_TXD */
+	/* F7  : CNV_RGI_DT_RSP_UART9_CTSB */
+	/* F8  : CNV_MFUART2_RXD */
+	PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1),
+	/* F9  : CNV_MFUART2_TXD */
+	PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1),
+	/* F10 : GPP_F_10 */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+	/* F11 : EMMC_CMD */
+	/* F12 : EMMC_DATA0 */
+	/* F13 : EMMC_DATA1 */
+	/* F14 : EMMC_DATA2 */
+	/* F15 : EMMC_DATA3 */
+	/* F16 : EMMC_DATA4 */
+	/* F17 : EMMC_DATA5 */
+	/* F18 : EMMC_DATA6 */
+	/* F19 : EMMC_DATA9 */
+	/* F20 : EMMC_RCLK */
+	/* F21 : EMMC_CLK */
+	/* F22 : EMMC_RESETB */
+	/* F23 : BIOS_REC */
+	PAD_CFG_GPI(GPP_F23, UP_20K, DEEP),
+	/* G0  : SD3_D2 */
+	/* G1  : SD3_D0_SD4_RCLK_P */
+	/* G2  : SD3_D1_SD4_RCLK_N */
+	/* G3  : SD3_D2 */
+	/* G4  : SD3_D3 */
+	/* G5  : SD3_CDB */
+	PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1),
+	/* G6  : SD3_CLK */
+	/* G7  : SD3_WP */
+	PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
+
+	/* H0  : SSP2_SCLK */
+	/* H1  : SSP2_SFRM */
+	/* H2  : SSP2_TXD */
+	/* H3  : SSP2_RXD */
+	/* H4  : I2C2_SDA */
+	/* H5  : I2C2_SCL */
+	/* H6  : I2C3_SDA */
+	PAD_CFG_NF(GPP_H6, UP_2K, DEEP, NF1),
+	/* H7  : I2C3_SCL */
+	PAD_CFG_NF(GPP_H7, UP_2K, DEEP, NF1),
+	/* H8  : I2C4_SDA */
+	/* H9  : I2C4_SCL */
+	/* H10 : I2C5_SDA_ISH_I2C2_SDA */
+	PAD_CFG_GPO(GPP_H10, 1, PLTRST),
+	/* H11 : I2C5_SCL_ISH_I2C2_SCL */
+	PAD_CFG_GPO(GPP_H11, 1, PLTRST),
+	/* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+	/* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+	/* H14 : M2_SKT2_CFG_2 */
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+	/* H15 : M2_SKT2_CFG_3 */
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+	/* H16 : CAM5_PWR_EN */
+	PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+	/* H17 : CAM5_FLASH_STROBE */
+	PAD_CFG_GPO(GPP_H17, 1, PLTRST),
+	/* H18 : BOOTMPC */
+	/* H19 : TIMESYNC_0 */
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+	/* H20 : IMGCLKOUT_1 */
+	/* H21 : GPPC_H_21 */
+	/* H22 : GPPC_H_22 */
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+	/* H23 : GPPC_H_23 */
+
+	/* GPD */
+	/* GPD_0  : BATLOWB */
+	/* GPD_1  : ACPRESENT */
+	/* GPD_2  : LAN_WAKEB */
+	/* GPD_3  : PWRBTNB */
+	/* GPD_4  : SLP_S3B */
+	/* GPD_5  : SLP_S4B */
+	/* GPD_6  : SLP_AB */
+	/* GPD_7  : GPD_7 */
+	/* GPD-8  : SUSCLK */
+	/* GPD-9  : SLP_WLANB */
+	/* GPD-10 : SLP_5B */
+	/* GPD_11 : LANPHYPC */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+};
+
+const struct pad_config *__weak variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak
+	variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio * __weak variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..36318d5ef7
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpio.h>
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..12d16bc72c
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
new file mode 100644
index 0000000000..426436ed4b
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
@@ -0,0 +1,144 @@
+chip soc/intel/icelake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "3"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpEnable[11]" = "1"
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpEnable[13]" = "1"
+	register "PcieRpEnable[14]" = "1"
+	register "PcieRpEnable[15]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "1"
+	register "PcieClkSrcUsage[1]" = "8"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+	register "PcieClkSrcUsage[3]" = "13"
+	register "PcieClkSrcUsage[4]" = "4"
+	register "PcieClkSrcUsage[5]" = "14"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| I2C3              | Audio                     |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.i2c[3] = {
+			.speed = I2C_SPEED_STANDARD,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+	}"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.3 on  end # CNVi wifi
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on  end # I2C #0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off end # I2C #2
+		device pci 15.3 on end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 off  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h
new file mode 100644
index 0000000000..c34a9b3cd9
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
new file mode 100644
index 0000000000..55b5aa34f1
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
@@ -0,0 +1,128 @@
+chip soc/intel/icelake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+	# FSP configuration
+	register "SaGv" = "3"
+	register "SmbusEnable" = "1"
+	register "ScsEmmcHs400Enabled" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)"
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"
+	register "usb2_ports[6]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[7]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[8]" = "USB2_PORT_EMPTY"
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"
+	register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"
+
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHda" = "1"
+	register "PchHdaAudioLinkSsp0" = "1"
+	register "PchHdaAudioLinkSsp1" = "1"
+
+	register "PcieRpEnable[0]" = "1"
+	register "PcieRpEnable[1]" = "1"
+	register "PcieRpEnable[2]" = "1"
+	register "PcieRpEnable[3]" = "1"
+	register "PcieRpEnable[4]" = "1"
+	register "PcieRpEnable[5]" = "1"
+	register "PcieRpEnable[6]" = "1"
+	register "PcieRpEnable[7]" = "1"
+	register "PcieRpEnable[8]" = "1"
+	register "PcieRpEnable[9]" = "1"
+	register "PcieRpEnable[10]" = "1"
+	register "PcieRpEnable[11]" = "1"
+	register "PcieRpEnable[12]" = "1"
+	register "PcieRpEnable[13]" = "1"
+
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[1]" = "8"
+	register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN"
+	register "PcieClkSrcUsage[3]" = "14"
+	register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
+	register "PcieClkSrcUsage[5]" = "1"
+
+	register "PcieClkSrcClkReq[0]" = "0"
+	register "PcieClkSrcClkReq[1]" = "1"
+	register "PcieClkSrcClkReq[2]" = "2"
+	register "PcieClkSrcClkReq[3]" = "3"
+	register "PcieClkSrcClkReq[4]" = "4"
+	register "PcieClkSrcClkReq[5]" = "5"
+
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
+	# GPIO for SD card detect
+	register "sdcard_cd_gpio" = "GPP_G5"
+
+	# Enable S0ix
+	register "s0ix_enable" = "1"
+
+	device domain 0 on
+		device pci 00.0 on  end # Host Bridge
+		device pci 02.0 on  end # Integrated Graphics Device
+		device pci 04.0 on  end # SA Thermal device
+		device pci 12.0 on  end # Thermal Subsystem
+		device pci 12.5 off end # UFS SCS
+		device pci 12.6 off end # GSPI #2
+		device pci 14.0 on  end # USB xHCI
+		device pci 14.1 off end # USB xDCI (OTG)
+		device pci 14.3 on  end # CNVi wifi
+		device pci 14.5 on  end # SDCard
+		device pci 15.0 on  end # I2C 0
+		device pci 15.1 on  end # I2C #1
+		device pci 15.2 off  end # I2C #2
+		device pci 15.3 on  end # I2C #3
+		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.1 off end # Management Engine Interface 2
+		device pci 16.2 off end # Management Engine IDE-R
+		device pci 16.3 off end # Management Engine KT Redirection
+		device pci 16.4 off end # Management Engine Interface 3
+		device pci 16.5 off end # Management Engine Interface 4
+		device pci 17.0 off  end # SATA
+		device pci 19.0 on  end # I2C #4
+		device pci 19.1 off end # I2C #5
+		device pci 19.2 on  end # UART #2
+		device pci 1a.0 on  end # eMMC
+		device pci 1c.0 on  end # PCI Express Port 1 x4 SLOT1
+		device pci 1c.4 on  end # PCI Express Port 5 x1 SLOT2/LAN
+		device pci 1c.5 off end # PCI Express Port 6
+		device pci 1c.6 off end # PCI Express Port 7
+		device pci 1c.7 off end # PCI Express Port 8
+		device pci 1d.0 on  end # PCI Express Port 9
+		device pci 1d.1 off end # PCI Express Port 10
+		device pci 1d.2 off end # PCI Express Port 11
+		device pci 1d.3 off end # PCI Express Port 12
+		device pci 1d.4 off end # PCI Express Port 13
+		device pci 1d.5 off end # PCI Express Port 14
+		device pci 1d.6 off end # PCI Express Port 15
+		device pci 1d.7 off end # PCI Express Port 16
+		device pci 1e.0 on  end # UART #0
+		device pci 1e.1 off end # UART #1
+		device pci 1e.2 off end # GSPI #0
+		device pci 1e.3 off end # GSPI #1
+		device pci 1f.0 on
+			chip drivers/pc80/tpm
+				device pnp 0c31.0 on end
+			end
+		end # LPC Interface
+		device pci 1f.1 on  end # P2SB
+		device pci 1f.2 on  end # Power Management Controller
+		device pci 1f.3 on  end # Intel HDA
+		device pci 1f.4 on  end # SMBus
+		device pci 1f.5 on  end # PCH SPI
+		device pci 1f.6 off end # GbE
+	end
+end
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h
new file mode 100644
index 0000000000..c34a9b3cd9
--- /dev/null
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+#endif /* __MAINBOARD_GPIO_H__ */