mainboard/intel/harcuvar: Add support for Intel Harcuvar CRB

The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.

Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>

4 files changed, 305 insertions, 0 deletions

diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard.asl b/src/mainboard/intel/harcuvar/acpi/mainboard.asl
new file mode 100644
index 0000000000..41da3824ef
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/acpi/mainboard.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+
+		// Wake
+		Name(_PRW, Package(){0x1d, 0x05})
+	}
+}
diff --git a/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl
new file mode 100644
index 0000000000..e253cea8a2
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/acpi/mainboard_pci_irqs.asl
@@ -0,0 +1,187 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* This is board specific information: IRQ routing */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// [GREG]: Global Registers
+			Package() { 0x0004ffff, 0, 0, 16 },
+
+			// [RCEC]: Root Complex Event Collector
+			Package() { 0x0005ffff, 0, 0, 23 },
+
+			// [VRP2]: Virtual root port 2
+			Package() { 0x0006ffff, 2, 0, 18 },
+
+			// [PEX0]: PCI Express Port 0
+			Package() { 0x0009ffff, 0, 0, 16 },
+
+			// [PEX1]: PCI Express Port 1
+			Package() { 0x000affff, 1, 0, 17 },
+
+			// [PEX2]: PCI Express Port 2
+			Package() { 0x000bffff, 2, 0, 18 },
+
+			// [PEX3]: PCI Express Port 3
+			Package() { 0x000cffff, 3, 0, 19 },
+
+			// [PEX4]: PCI Express Port 4
+			Package() { 0x000effff, 0, 0, 20 },
+
+			// [PEX5]: PCI Express Port 5
+			Package() { 0x000fffff, 1, 0, 21 },
+
+			// [PEX6]: PCI Express Port 6
+			Package() { 0x0010ffff, 2, 0, 22 },
+
+			// [PEX7]: PCI Express Port 7
+			Package() { 0x0011ffff, 3, 0, 23 },
+
+			// [SMB1]: SMBus controller
+			Package() { 0x0012ffff, 0, 0, 16 },
+
+			// [SAT0]: SATA controller 0
+			Package() { 0x0013ffff, 0, 0, 20 },
+
+			// [SAT1]: SATA controller 1
+			Package() { 0x0014ffff, 0, 0, 21 },
+
+			// [XHC0]: XHCI USB controller
+			Package() { 0x0015ffff, 0, 0, 19 },
+
+			// [VRP0]: Virtual root port 0
+			Package() { 0x0016ffff, 0, 0, 16 },
+
+			// [VRP1]: Virtual root port 1
+			Package() { 0x0017ffff, 1, 0, 17 },
+
+			// [HECI]: ME HECI
+			Package() { 0x0018ffff, 0, 0, 16 },
+
+			// [HEC2]: ME HECI2
+			Package() { 0x0018ffff, 1, 0, 17 },
+
+			// [MEKT]: MEKT on PCH
+			Package() { 0x0018ffff, 2, 0, 18 },
+
+			// [HEC3]: ME HECI3
+			Package() { 0x0018ffff, 3, 0, 19 },
+
+			// [UAR0]: UART 0
+			Package() { 0x001affff, 0, 0, 16 },
+
+			// [UAR1]: UART 1
+			Package() { 0x001affff, 1, 0, 17 },
+
+			// [UAR2]: UART 2
+			Package() { 0x001affff, 2, 0, 18 },
+
+			// [EMMC]: eMMC
+			Package() { 0x001cffff, 0, 0, 16 },
+
+			// [P2SB]: Primary to sideband bridge
+			// [SMB0]: SMBus controller
+			// [NPK0]: Northpeak DFX
+			Package() { 0x001fffff, 0, 0, 23 },
+		})
+	} Else {
+		Return (Package() {
+			// [GREG]: Global Registers		0:4.0
+			Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [RCEC]: Root Complex Event Collector		0:5.0
+			Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+
+			// [VRP2]: Virtual root port 2		0:6.0
+			Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [PEX0]: PCI Express Port 0		0:9.0
+			Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [PEX1]: PCI Express Port 1		0:a.0
+			Package() { 0x000affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [PEX2]: PCI Express Port 2		0:b.0
+			Package() { 0x000bffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [PEX3]: PCI Express Port 3		0:c.0
+			Package() { 0x000cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [PEX4]: PCI Express Port 4		0:e.0
+			Package() { 0x000effff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+			// [PEX5]: PCI Express Port 5		0:f.0
+			Package() { 0x000fffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+
+			// [PEX6]: PCI Express Port 6		0:10.0
+			Package() { 0x0010ffff, 2, \_SB.PCI0.LPCB.LNKG, 0 },
+
+			// [PEX7]: PCI Express Port 7		0:11.0
+			Package() { 0x0011ffff, 3, \_SB.PCI0.LPCB.LNKH, 0 },
+
+			// [SMB1]: SMBus controller		0:12.0
+			Package() { 0x0012ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [SAT0]: SATA controller 0		0:13.0
+			Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+
+			// [SAT1]: SATA controller 1		0:14.0
+			Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+
+			// [XHC0]: XHCI USB controller		0:15.0
+			Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [VRP0]: Virtual root port 0		0:16.0
+			Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [VRP1]: Virtual root port 1		0:17.0
+			Package() { 0x0017ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [HECI]: ME HECI		0:18.0
+			Package() { 0x0018ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [HEC2]: ME HECI2		0:18.1
+			Package() { 0x0018ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [MEKT]: MEKT on PCH		0:18.2
+			Package() { 0x0018ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [HEC3]: ME HECI3		0:18.3
+			Package() { 0x0018ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+
+			// [UAR0]: UART 0		0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [UAR1]: UART 1		0:1a.1
+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+
+			// [UAR2]: UART 2		0:1a.2
+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			// [EMMC]: eMMC		0:1c.0
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+
+			// [P2SB]: Primary to sideband bridge
+			// [SMB0]: SMBus controller
+			// [NPK0]: Northpeak DFX
+			Package() { 0x001ffffF, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+		})
+	}
+}
diff --git a/src/mainboard/intel/harcuvar/acpi/platform.asl b/src/mainboard/intel/harcuvar/acpi/platform.asl
new file mode 100644
index 0000000000..ea66a9f974
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/acpi/platform.asl
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 - 2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
diff --git a/src/mainboard/intel/harcuvar/acpi/thermal.asl b/src/mainboard/intel/harcuvar/acpi/thermal.asl
new file mode 100644
index 0000000000..5f9164da0d
--- /dev/null
+++ b/src/mainboard/intel/harcuvar/acpi/thermal.asl
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 - 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+ // Thermal Zone
+
+Scope (\_TZ)
+{
+}