diff options
author | Aaron Durbin <adurbin@chromium.org> | 2012-11-29 17:18:53 -0600 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 05:07:43 +0100 |
commit | 8256a9b715df14dc8914b641796344ac513cb889 (patch) | |
tree | 5c18aa2a2d0a45b93b2b6124dfd4529485702cb6 /src/mainboard/intel/graysreef/romstage.c | |
parent | b9adf7ba4bf6e8f11bf174973230c5317cbb3b6d (diff) |
haswell: align pei_data structure with intel-framework
The intel-framework code has an updated pei_data structure.
Use the new structure and revision. Also, remove the scrambler
seed saving in CMOS since that appears to be handled in the saved
data from the reference code.
Change-Id: Ie09a0a00646ab040e8ceff922048981d055d5cd2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2630
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/graysreef/romstage.c')
-rw-r--r-- | src/mainboard/intel/graysreef/romstage.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mainboard/intel/graysreef/romstage.c b/src/mainboard/intel/graysreef/romstage.c index 6e35d51bf8..da839f41c8 100644 --- a/src/mainboard/intel/graysreef/romstage.c +++ b/src/mainboard/intel/graysreef/romstage.c @@ -143,11 +143,10 @@ void main(unsigned long bist) rcba: DEFAULT_RCBA, pmbase: DEFAULT_PMBASE, gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, + temp_mmio_base: 0xfed08000, system_type: 0, // 0 Mobile, 1 Desktop/Server tseg_size: CONFIG_SMM_TSEG_SIZE, spd_addresses: { 0xa0, 0x00, 0xa4, 0x00 }, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, ec_present: 0, // 0 = leave channel enabled // 1 = disable dimm 0 on channel |