diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-03-12 14:32:26 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-14 18:27:02 +0100 |
| commit | e265d209374812f103fa401be518db624b79520d (patch) | |
| tree | 16bd6ec8759e0205c3fe5273913892fee6cf1b1e /src/mainboard/intel/graysreef/dsdt.asl | |
| parent | 74c0d05cf51e089357712b2c855f344caba680fb (diff) | |
baskingridge: rename graysreef to baskingridge
The Grays Reef CRB is deprecated by order of Intel. Basking Ridge
is the new hotness. Therefore, rename graysreef to basking ridge.
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I203497e165d8efc99d3438c4c548140a6e9cc649
Reviewed-on: http://review.coreboot.org/2672
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/intel/graysreef/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/graysreef/dsdt.asl | 56 |
1 files changed, 0 insertions, 56 deletions
diff --git a/src/mainboard/intel/graysreef/dsdt.asl b/src/mainboard/intel/graysreef/dsdt.asl deleted file mode 100644 index 79bb8f39f8..0000000000 --- a/src/mainboard/intel/graysreef/dsdt.asl +++ /dev/null @@ -1,56 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include "acpi/platform.asl" - - // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> - - // General Purpose Events - //#include "acpi/gpe.asl" - - #include "acpi/thermal.asl" - - #include "../../../cpu/intel/haswell/acpi/cpu.asl" - - Scope (\_SB) { - Device (PCI0) - { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> - } - } - - #include "acpi/chromeos.asl" - #include <vendorcode/google/chromeos/acpi/chromeos.asl> - - /* Chipset specific sleep states */ - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> -} |