diff options
author | Aaron Durbin <adurbin@chromium.org> | 2012-10-30 09:09:39 -0500 |
---|---|---|
committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 05:06:56 +0100 |
commit | f6933a6f56f8bdc7e249b6629824acce646d5f6a (patch) | |
tree | 46ce97c68b1b417fb78ecc007c8c63f9f2b502ac /src/mainboard/intel/graysreef/acpi/superio.asl | |
parent | ce36b12c2702d88e95e5c0294035bcd5e1de22ab (diff) |
Mainboard: Add support for Grays Reef
Grays Reef is one of Intel's CRBs for the Haswell processor. The
platform is named Shark Bay.
GPIOs were the main focus so IRQ routing and ACPI still needs to be
further looked at.
Change-Id: Ie94b7af66f772714992a92612c76ca93b9b27088
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2621
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel/graysreef/acpi/superio.asl')
-rw-r--r-- | src/mainboard/intel/graysreef/acpi/superio.asl | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/mainboard/intel/graysreef/acpi/superio.asl b/src/mainboard/intel/graysreef/acpi/superio.asl new file mode 100644 index 0000000000..a50c4b3aa3 --- /dev/null +++ b/src/mainboard/intel/graysreef/acpi/superio.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#define SIO_ENABLE_PS2K // pnp 2e.5: Enable PS/2 Keyboard +#define SIO_ENABLE_PS2M // pnp 2e.6: Enable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/smsc/sio1007/acpi/superio.asl" |