diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2017-08-29 15:42:27 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-14 20:12:50 +0000 |
| commit | 73f073d393c8cf3064434192fd0237a5ecd30de4 (patch) | |
| tree | 49cdcdfaffc7c4efcfe766365df2adf060b53b70 /src/mainboard/intel/glkrvp | |
| parent | ff3162b5e4c179b1b79c4acd5eb82bae6eee495e (diff) | |
mainboard/intel/glkrvp: Configure Prmrr and Enable SGX
Configure PRMRR to allocate 128MiB for SGX enclave memory and enable SGX
by default for GLKRVP platform.
Supported PRMRR size options:
0x02000000 - 32MiB
0x04000000 - 64MiB
0x08000000 - 128MiB
Change-Id: Ifa39df4a1da84bae49551a9626257bda0729752b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/glkrvp')
| -rw-r--r-- | src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index c0831459bd..45badcddbd 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -90,6 +90,14 @@ chip soc/intel/apollolake # Minimum SLP S3 assertion width 28ms. register "slp_s3_assertion_width_usecs" = "28000" + register "sgx_enable" = "1" + + # PRMRR size options + # 0x02000000 - 32MiB + # 0x04000000 - 64MiB + # 0x08000000 - 128MiB + register "PrmrrSize" = "128 * MiB" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF |