diff options
author | Hannah Williams <hannah.williams@intel.com> | 2017-05-05 16:39:21 -0700 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-26 20:31:24 +0000 |
commit | d59f62bbdabeb98f12896c6af0ef50cbf25e013f (patch) | |
tree | ee22acd54dce71c326c019ee41f86c310f2b0df6 /src/mainboard/intel/glkrvp/mainboard.c | |
parent | 50ab84fa370ac247dfe57a65f9d9b1ed0384e7fa (diff) |
mainboard/intel/glkrvp: Add support for GLKRVP
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/glkrvp/mainboard.c')
-rw-r--r-- | src/mainboard/intel/glkrvp/mainboard.c | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/src/mainboard/intel/glkrvp/mainboard.c b/src/mainboard/intel/glkrvp/mainboard.c new file mode 100644 index 0000000000..ac5e973168 --- /dev/null +++ b/src/mainboard/intel/glkrvp/mainboard.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <console/console.h> +#include <device/device.h> +#include <ec/ec.h> +#include <nhlt.h> +#include <soc/gpio.h> +#include <soc/nhlt.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <variant/ec.h> +#include <variant/gpio.h> + +static void mainboard_init(void *chip_info) +{ + int boardid; + const struct pad_config *pads; + size_t num; + + boardid = board_id(); + printk(BIOS_INFO, "Board ID: %d\n", boardid); + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); + + mainboard_ec_init(); +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; |