diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-18 18:52:43 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-08 17:59:20 +0200 |
| commit | dc542702108fc80997f074978ac404c83ee0e9bf (patch) | |
| tree | a25026af01a13f461e29c8a01848f617d7580ae3 /src/mainboard/intel/galileo | |
| parent | 5d94c2665360aad315b494b9ed47ed7f33a695a5 (diff) | |
soc/intel/quark: Pass in the memory initialization parameters
Specify the memory initialization parameters in
mainboard/intel/galileo/devicetree.cb. Pass these values into FSP to
initialize memory.
TEST=Build and run on Galileo Gen2
Change-Id: I83ee196f5fb825118a3a74b61f73f3728a1a1dc6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15260
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/galileo')
| -rw-r--r-- | src/mainboard/intel/galileo/devicetree.cb | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index fcc0dae526..f7d666d6f5 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -20,7 +20,32 @@ chip soc/intel/quark # Set the parameters for MemoryInit ############################################################ - register "PcdSmmTsegSize" = "0" # SMM Region size in MiB + register "AddrMode" = "0" + register "ChanMask" = "1" # Channel 0 enabled + register "ChanWidth" = "1" # 16-bit channel + register "DramDensity" = "1" # 1 Gib; + register "DramRonVal" = "0" # 34 Ohm + register "DramRttNomVal" = "2" # 120 Ohm + register "DramRttWrVal" = "0" # off + register "DramSpeed" = "0" # 800 MHz + register "DramType" = "0" # DDR3 + register "DramWidth" = "0" # 8-bit + register "EccScrubBlkSize" = "2" # 64 byte blocks + register "EccScrubInterval" = "0" # ECC scrub disabled + register "Flags" = "MRC_FLAG_SCRAMBLE_EN" + register "FspReservedMemoryLength" = "0x00100000" # Size in bytes + register "RankMask" = "1" # RANK 0 enabled + register "SmmTsegSize" = "0" # SMM Region size in MiB + register "SocRdOdtVal" = "0" # off + register "SocWrRonVal" = "1" # 32 Ohm + register "SocWrSlewRate" = "1" # 4V/nSec + register "SrInt" = "3" # 7.8 uSec + register "SrTemp" = "0" # normal + register "tCL" = "6" # clocks + register "tFAW" = "40000" # picoseconds + register "tRAS" = "37500" # picoseconds + register "tRRD" = "10000" # picoseconds + register "tWTR" = "10000" # picoseconds ############################################################ # Enable the devices |