diff options
| author | Joey Peng <joey.peng@lcfc.corp-partner.google.com> | 2021-12-17 12:52:43 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-23 14:34:00 +0000 |
| commit | 591789b50bc8a2ef3f679d7790397b6eaabfae09 (patch) | |
| tree | 3c1fd3cd58c46992719c65ac51a75fa9a9bb143b /src/mainboard/intel/galileo | |
| parent | 0afecdf95add5cc0167d85b9dd9bcad503d9358f (diff) | |
mb/google/brya/var/taeko4es: Fix PLD group order (W/A)
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/galileo')
0 files changed, 0 insertions, 0 deletions