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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-15 13:52:36 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-17 23:30:09 +0200 |
| commit | 274d20a0652f45ed54834524c485f7ab59bcdf70 (patch) | |
| tree | b3e35b64d328f752cdff20108202551a1e417f65 /src/mainboard/intel/galileo/gen1.h | |
| parent | 0ba307f0fe94550d84499562fb8f238f770aae3f (diff) | |
mainboard/intel/galileo: Add GPIO initialization
Add Kconfig to configure coreboot for a specific Galileo board.
Configure the GPIOs for the specific Galileo board.
TEST=Build and run on Galileo Gen2
Change-Id: I992460d506b5543915c27f6a531da4b1a53d6505
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14826
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/galileo/gen1.h')
| -rw-r--r-- | src/mainboard/intel/galileo/gen1.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h new file mode 100644 index 0000000000..c718b617a8 --- /dev/null +++ b/src/mainboard/intel/galileo/gen1.h @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +static const struct reg_script gen1_gpio_init[] = { + /* Initialize the legacy GPIO controller */ + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00), + + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f), + REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00), + + /* Initialize the GPIO controller */ + REG_GPIO_WRITE(GPIO_INTEN, 0), + REG_GPIO_WRITE(GPIO_INTSTATUS, 0), + REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5), + REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15), + REG_GPIO_WRITE(GPIO_INTMASK, 0), + REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0), + REG_GPIO_WRITE(GPIO_INT_POLARITY, 0), + REG_GPIO_WRITE(GPIO_DEBOUNCE, 0), + REG_GPIO_WRITE(GPIO_LS_SYNC, 0), + + /* Toggle the Cypress reset line */ + REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4), + REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4), + REG_SCRIPT_END +}; |