diff options
| author | Felix Singer <felixsinger@posteo.net> | 2023-05-19 15:28:58 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-05-20 16:27:07 +0000 |
| commit | 037c25d4dd8dda28da64af1e29e787fb8b55c84b (patch) | |
| tree | fcd47eb096a58146d3efe4c22be6e0ebdefd0dcc /src/mainboard/intel/galileo/devicetree.cb | |
| parent | 4265d5265dfc7bd823bcf5c8c5dded8d06189f69 (diff) | |
mb/intel/galileo: Drop support
As announced in the 4.20 release notes, support for the Intel Galileo
mainboard is moved to the 4.20 branch and dropped from master.
Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/mainboard/intel/galileo/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/galileo/devicetree.cb | 58 |
1 files changed, 0 insertions, 58 deletions
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb deleted file mode 100644 index 4a806431ab..0000000000 --- a/src/mainboard/intel/galileo/devicetree.cb +++ /dev/null @@ -1,58 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/intel/quark - - ############################################################ - # Set the parameters for MemoryInit - ############################################################ - - register "AddrMode" = "0" - register "ChanMask" = "1" # Channel 0 enabled - register "ChanWidth" = "1" # 16-bit channel - register "DramDensity" = "1" # 1 Gib; - register "DramRonVal" = "0" # 34 Ohm - register "DramRttNomVal" = "2" # 120 Ohm - register "DramRttWrVal" = "0" # off - register "DramSpeed" = "0" # 800 MHz - register "DramType" = "0" # DDR3 - register "DramWidth" = "0" # 8-bit - register "EccScrubBlkSize" = "2" # 64 byte blocks - register "EccScrubInterval" = "0" # ECC scrub disabled - register "Flags" = "MRC_FLAG_SCRAMBLE_EN" - register "FspReservedMemoryLength" = "0x00100000" # Size in bytes - register "RankMask" = "1" # RANK 0 enabled - register "SmmTsegSize" = "0" # SMM Region size in MiB - register "SocRdOdtVal" = "0" # off - register "SocWrRonVal" = "1" # 32 Ohm - register "SocWrSlewRate" = "1" # 4V/nSec - register "SrInt" = "3" # 7.8 uSec - register "SrTemp" = "0" # normal - register "tCL" = "6" # clocks - register "tFAW" = "40000" # picoseconds - register "tRAS" = "37500" # picoseconds - register "tRRD" = "10000" # picoseconds - register "tWTR" = "10000" # picoseconds - - ############################################################ - # Enable the devices - ############################################################ - - device domain 0 on - # EDS Table 3 - device pci 00.0 on end # 8086 0958 - Host Bridge - device pci 14.0 on end # 8086 08A7 - SD/SDIO/eMMC controller - device pci 14.1 off end # 8086 0936 - HSUART 0 - device pci 14.2 on end # 8086 0939 - USB 2.0 Device port - device pci 14.3 on end # 8086 0939 - USB EHCI Host controller - device pci 14.4 on end # 8086 093A - USB OHCI Host controller - device pci 14.5 on end # 8086 0936 - HSUART 1 - device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 - device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 - device pci 15.0 on end # 8086 0935 - SPI controller 0 - device pci 15.1 on end # 8086 0935 - SPI controller 1 - device pci 15.2 on end # 8086 0934 - I2C/GPIO controller - device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 - device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1 - device pci 1f.0 on end # 8086 095E - Legacy Bridge - end -end |