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authorKane Chen <kane.chen@intel.com>2016-07-11 12:17:13 +0800
committerAaron Durbin <adurbin@chromium.org>2016-07-15 18:20:54 +0200
commitd779605c29a1630a256c8a1c4966214c580481ec (patch)
tree7a256924f020fe35004cb4288bd126fb116ac5c5 /src/mainboard/intel/galileo/Kconfig
parent97fc426070887ecfcaf3988ea8df02d1c682317a (diff)
soc/intel/apollolake: Properly disable PCIe root ports
1. The hotplug feature needs to be disabled so that pcie root ports will be disabled by fsp 2. Correct PcieRootPortEn mapping. The correct mapping should be like below PcieRootPortEn[0] ==> 00:14.0 PcieRootPortEn[1] ==> 00:14.1 PcieRootPortEn[2] ==> 00:13.0 PcieRootPortEn[3] ==> 00:13.1 PcieRootPortEn[4] ==> 00:13.2 PcieRootPortEn[5] ==> 00:13.3 BUG=chrome-os-partner:54288 BRANCH=None TEST=Checked pcie root port is disabled properly and make sure pcie ports are coalesced. Also make sure the device will still be enabled after coalescence when pcie on function 0 is disabled devicetree Change-Id: I39c482a0c068ddc2cc573499480c3fe6a52dd5eb Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/15595 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel/galileo/Kconfig')
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