diff options
author | Vladimir Serbinenko <phcoder@gmail.com> | 2016-02-10 01:43:08 +0100 |
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committer | Martin Roth <martinroth@google.com> | 2016-02-12 04:22:00 +0100 |
commit | 613d3ad2086f463170fc0791653532abc937dc9c (patch) | |
tree | 2a9b22fb10341443ed5cfeda6e272a7e22f4ed77 /src/mainboard/intel/emeraldlake2/gpio.c | |
parent | ffbb3c0b8abea621eb7a1583d630cf06c8cbfbbc (diff) |
Move gpio.h to gpio.c on sandy and ivy.
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13657
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2/gpio.c')
-rw-r--r-- | src/mainboard/intel/emeraldlake2/gpio.c | 102 |
1 files changed, 102 insertions, 0 deletions
diff --git a/src/mainboard/intel/emeraldlake2/gpio.c b/src/mainboard/intel/emeraldlake2/gpio.c new file mode 100644 index 0000000000..37b2430aea --- /dev/null +++ b/src/mainboard/intel/emeraldlake2/gpio.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef EMERALDLAKE2_GPIO_H +#define EMERALDLAKE2_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio36 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio48 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif |