summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/emeraldlake2/acpi
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2020-10-08 09:38:36 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-11-04 09:41:27 +0000
commit2f1b51ac2b4b11866ae998cc09bfc6273edb2f14 (patch)
treef04bcd33984f72414315a45160e8e1c97722da13 /src/mainboard/intel/emeraldlake2/acpi
parente28133a9948df5f98007219d54d1afa478318d56 (diff)
mb/intel/emeraldlake2: Convert to ASL 2.0 syntax
Generated 'build/dsdt.dsl' files are identical. Change-Id: Idd2bf447975b4c9b2cd3b440505c0bd960374165 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/emeraldlake2/acpi')
-rw-r--r--src/mainboard/intel/emeraldlake2/acpi/platform.asl8
-rw-r--r--src/mainboard/intel/emeraldlake2/acpi/thermal.asl74
2 files changed, 41 insertions, 41 deletions
diff --git a/src/mainboard/intel/emeraldlake2/acpi/platform.asl b/src/mainboard/intel/emeraldlake2/acpi/platform.asl
index 9568641fcf..9858fda223 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/platform.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/platform.asl
@@ -8,16 +8,16 @@ Method(_PTS,1)
{
// NVS has a flag to determine USB policy in S3
if (S3U0) {
- Store (One, GP47) // Enable USB0
+ GP47 = 1 // Enable USB0
} Else {
- Store (Zero, GP47) // Disable USB0
+ GP47 = 0 // Disable USB0
}
// NVS has a flag to determine USB policy in S3
if (S3U1) {
- Store (One, GP56) // Enable USB1
+ GP56 = 1 // Enable USB1
} Else {
- Store (Zero, GP56) // Disable USB1
+ GP56 = 0 // Disable USB1
}
}
diff --git a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
index 39d61b2a13..0a3bb49732 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/thermal.asl
@@ -21,10 +21,10 @@ Scope (\_TZ)
// Convert from Degrees C to 1/10 Kelvin for ACPI
Method (CTOK, 1) {
// 10th of Degrees C
- Multiply (Arg0, 10, Local0)
+ Local0 = Arg0 * 10
// Convert to Kelvin
- Add (Local0, 2732, Local0)
+ Local0 += 2732
Return (Local0)
}
@@ -50,28 +50,28 @@ Scope (\_TZ)
Method (_TMP, 0, Serialized)
{
// Get CPU Temperature from PECI via SuperIO TMPIN3
- Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+ Local0 = \_SB.PCI0.LPCB.SIO.ENVC.TIN3
// Check for invalid readings
- If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+ If ((Local0 == 255) || (Local0 == 0)) {
Return (CTOK (\F2ON))
}
// PECI raw value is an offset from Tj_max
- Subtract (255, Local0, Local1)
+ Local1 = 255 - Local0
// Handle values greater than Tj_max
- If (LGreaterEqual (Local1, \TMAX)) {
+ If (Local1 >= \TMAX) {
Return (CTOK (\TMAX))
}
// Subtract from Tj_max to get temperature
- Subtract (\TMAX, Local1, Local0)
+ Local0 = \TMAX - Local1
Return (CTOK (Local0))
}
Method (_AC0) {
- If (LLessEqual (\FLVL, 0)) {
+ If (\FLVL <= 0) {
Return (CTOK (\F0OF))
} Else {
Return (CTOK (\F0ON))
@@ -79,7 +79,7 @@ Scope (\_TZ)
}
Method (_AC1) {
- If (LLessEqual (\FLVL, 1)) {
+ If (\FLVL <= 1) {
Return (CTOK (\F1OF))
} Else {
Return (CTOK (\F1ON))
@@ -87,7 +87,7 @@ Scope (\_TZ)
}
Method (_AC2) {
- If (LLessEqual (\FLVL, 2)) {
+ If (\FLVL <= 2) {
Return (CTOK (\F2OF))
} Else {
Return (CTOK (\F2ON))
@@ -95,7 +95,7 @@ Scope (\_TZ)
}
Method (_AC3) {
- If (LLessEqual (\FLVL, 3)) {
+ If (\FLVL <= 3) {
Return (CTOK (\F3OF))
} Else {
Return (CTOK (\F3ON))
@@ -103,7 +103,7 @@ Scope (\_TZ)
}
Method (_AC4) {
- If (LLessEqual (\FLVL, 4)) {
+ If (\FLVL <= 4) {
Return (CTOK (\F4OF))
} Else {
Return (CTOK (\F4ON))
@@ -119,20 +119,20 @@ Scope (\_TZ)
PowerResource (FNP0, 0, 0)
{
Method (_STA) {
- If (LLessEqual (\FLVL, 0)) {
+ If (\FLVL <= 0) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
- Store (0, \FLVL)
- Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 0
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F0PW
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 1
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW
Notify (\_TZ.THRM, 0x81)
}
}
@@ -140,20 +140,20 @@ Scope (\_TZ)
PowerResource (FNP1, 0, 0)
{
Method (_STA) {
- If (LLessEqual (\FLVL, 1)) {
+ If (\FLVL <= 1) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
- Store (1, \FLVL)
- Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 1
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F1PW
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 2
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW
Notify (\_TZ.THRM, 0x81)
}
}
@@ -161,20 +161,20 @@ Scope (\_TZ)
PowerResource (FNP2, 0, 0)
{
Method (_STA) {
- If (LLessEqual (\FLVL, 2)) {
+ If (\FLVL <= 2) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
- Store (2, \FLVL)
- Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 2
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F2PW
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 3
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW
Notify (\_TZ.THRM, 0x81)
}
}
@@ -182,20 +182,20 @@ Scope (\_TZ)
PowerResource (FNP3, 0, 0)
{
Method (_STA) {
- If (LLessEqual (\FLVL, 3)) {
+ If (\FLVL <= 3) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
- Store (3, \FLVL)
- Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 3
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F3PW
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 4
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
Notify (\_TZ.THRM, 0x81)
}
}
@@ -203,20 +203,20 @@ Scope (\_TZ)
PowerResource (FNP4, 0, 0)
{
Method (_STA) {
- If (LLessEqual (\FLVL, 4)) {
+ If (\FLVL <= 4) {
Return (One)
} Else {
Return (Zero)
}
}
Method (_ON) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 4
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
Notify (\_TZ.THRM, 0x81)
}
Method (_OFF) {
- Store (4, \FLVL)
- Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+ \FLVL = 4
+ \_SB.PCI0.LPCB.SIO.ENVC.F3PS = \F4PW
Notify (\_TZ.THRM, 0x81)
}
}