mb/intel/ehlcrb: Add EHL CRB memory initialization support

Update memory parameters based on memory type supported by
Elkhart Lake CRB:

1. Update spd data for EHL LPDDR4X memory
   - DQ byte map
   - DQS CPU-DRAM map
   - Rcomp resistor
   - Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
   initialization

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 11 insertions, 1 deletions

diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
index 481ff0939a..324083411c 100644
--- a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
+++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
@@ -7,5 +7,15 @@
 
 void mainboard_memory_init_params(FSPM_UPD *memupd)
 {
-	/* ToDo : Fill FSP-M spd related memory params */
+	static struct spd_info ehlcrb_spd_info;
+	const struct mb_cfg *board_cfg = variant_memcfg_config();
+
+	/* TODO: Read the resistor strap to get number of memory segments */
+	bool half_populated = false;
+	/* Initialize spd information for LPDDR4x board */
+	ehlcrb_spd_info.read_type = READ_SPD_CBFS;
+	ehlcrb_spd_info.spd_spec.spd_index = 0x00;
+
+	/* Initialize variant specific configurations */
+	memcfg_init(&memupd->FspmConfig, board_cfg, &ehlcrb_spd_info, half_populated);
 }