mb/intel/ehlcrb: Add initial mainboard code

This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.

This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868

List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/src/mainboard/intel/elkhartlake_crb/chromeos.fmd b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd
new file mode 100644
index 0000000000..05f45922e2
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/chromeos.fmd
@@ -0,0 +1,43 @@
+FLASH@0xff000000 0x1000000 {
+	SI_ALL@0x0 0x600000 {
+		SI_DESC@0x0 0x1000
+		SI_EC@0x1000 0x80000
+		SI_ME@0x81000 0x57F000
+	}
+	SI_BIOS@0x600000 0xA00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG(PRESERVE)@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD(PRESERVE)@0x28000 0x2000
+			RW_NVRAM(PRESERVE)@0x2a000 0x6000
+		}
+		RW_LEGACY(CBFS)@0x5d0000 0x30000
+		WP_RO@0x600000 0x400000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0x3fc000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0x3000
+				COREBOOT(CBFS)@0x4000 0x3f8000
+			}
+		}
+	}
+}