mb/intel/ehlcrb: Add initial mainboard code

This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.

This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868

List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
   config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs
 2. Clean up devicetree as per tigerlake SOC
 3. Add GPIO support
 4. Update ehl fmd file to replace 32MB chromeos.fmd

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

1 files changed, 71 insertions, 0 deletions

diff --git a/src/mainboard/intel/elkhartlake_crb/Kconfig b/src/mainboard/intel/elkhartlake_crb/Kconfig
new file mode 100644
index 0000000000..14c2b93347
--- /dev/null
+++ b/src/mainboard/intel/elkhartlake_crb/Kconfig
@@ -0,0 +1,71 @@
+if BOARD_INTEL_ELKHARTLAKE_CRB
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_16384
+	select DPTF_USE_EISA_HID
+	select DRIVERS_I2C_DA7219
+	select DRIVERS_I2C_HID
+	select DRIVERS_INTEL_DPTF
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_I2C_MAX98373
+	select DRIVERS_INTEL_MIPI_CAMERA
+	select DRIVERS_SPI_ACPI
+	select DRIVERS_USB_ACPI
+	select EC_ACPI
+	select HAVE_SPD_IN_CBFS
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select SOC_INTEL_COMMON_BLOCK_IPU
+	select SOC_INTEL_ELKHARTLAKE
+	select SOC_INTEL_COMMON_BLOCK_DTT
+	select SOC_INTEL_CSE_LITE_SKU
+
+config MAINBOARD_DIR
+	string
+	default "intel/elkhartlake_crb"
+
+config VARIANT_DIR
+	string
+	default "ehlcrb" if BOARD_INTEL_ELKHARTLAKE_CRB
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "ehlcrb"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_ehlcrb"
+
+config DEVICETREE
+	string
+	default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config CHROMEOS
+	bool
+	default y
+	select GBB_FLAG_FORCE_DEV_SWITCH_ON
+	select GBB_FLAG_FORCE_DEV_BOOT_USB
+	select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+	select GBB_FLAG_FORCE_MANUAL_RECOVERY
+	select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
+	select HAS_RECOVERY_MRC_CACHE
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
+
+config UART_FOR_CONSOLE
+	int
+	default 2 if INTEL_LPSS_UART_FOR_CONSOLE
+	default 0
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 45  # GPE0_DW1_13 (GPP_H13)
+endif