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authorWerner Zeh <werner.zeh@siemens.com>2016-09-08 07:27:29 +0200
committerWerner Zeh <werner.zeh@siemens.com>2016-09-12 06:33:53 +0200
commit91aea428b5932c031b81a6c4921ac416f2b2c995 (patch)
tree4290e161963bfc1ca1f31d3d668b619a90ded5ca /src/mainboard/intel/eagleheights/mptable.c
parentba349ab12eb5c6848d7e3b727d6fcd7fbe616614 (diff)
fsp_broadwell_de: Correct access to SIRQ_CNTL register
The serial IRQ configuration register is only 8 bit wide so switch the PCI access from 16 bits to 8 bits. Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16534 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/eagleheights/mptable.c')
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