mb/intel/dg43gt: Add mainboard

This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.

What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
  bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
  working gbe in this configuration though)
* USB.

What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
  BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)

Not tested:
* Sound;
* All the rest.

Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
  desoldering flash chip;
* In situ programming is not possible.

TESTED with SeaBIOS and Linux 4.10.8

Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

5 files changed, 170 insertions, 0 deletions

diff --git a/src/mainboard/intel/dg43gt/acpi/ec.asl b/src/mainboard/intel/dg43gt/acpi/ec.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000000..19882b87d0
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+	Return (Package() {
+		/* PCI slot */
+		Package() { 0x0000ffff, 0, 0, 0x15},
+		Package() { 0x0000ffff, 1, 0, 0x16},
+		Package() { 0x0000ffff, 2, 0, 0x17},
+		Package() { 0x0000ffff, 3, 0, 0x14},
+
+		Package() { 0x0004ffff, 0, 0, 0x16},
+		Package() { 0x0004ffff, 1, 0, 0x17},
+		Package() { 0x0004ffff, 2, 0, 0x14},
+		Package() { 0x0004ffff, 3, 0, 0x15},
+
+		Package() { 0x0006ffff, 0, 0, 0x17},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+	})
+}
diff --git a/src/mainboard/intel/dg43gt/acpi/platform.asl b/src/mainboard/intel/dg43gt/acpi/platform.asl
new file mode 100644
index 0000000000..6c92a4ed47
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/platform.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Method(_PIC, 1)
+{
+	/* Remember the OS' IRQ routing choice.  */
+	Store(Arg0, PICM)
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	/* SMI Function */
+	Store (0, TRP0)		/* Generate trap */
+	Return (SMIF)		/* Return value of SMI handler */
+}
diff --git a/src/mainboard/intel/dg43gt/acpi/superio.asl b/src/mainboard/intel/dg43gt/acpi/superio.asl
new file mode 100644
index 0000000000..2997587d82
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
new file mode 100644
index 0000000000..510af9abb6
--- /dev/null
+++ b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for x4x */
+/* Uses reset defaults + some undocumented device taken from vendor DSDT*/
+
+/* PCI Interrupt Routing */
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			/* PEG */
+			Package() { 0x0001ffff, 0, 0, 0x10 },
+			/* Internal GFX */
+			Package() { 0x0002ffff, 0, 0, 0x10 },
+			/* ME */
+			Package() { 0x0003ffff, 0, 0, 0x10 },
+			Package() { 0x0003ffff, 1, 0, 0x11 },
+			Package() { 0x0003ffff, 2, 0, 0x12 },
+			/* ?? */
+			Package() { 0x0016ffff, 0, 0, 0x12 },
+			Package() { 0x0016ffff, 1, 0, 0x13 },
+			/* GBE 	    		        0:19.0 */
+			Package() { 0x0019ffff, 0, 0, 0x10 },
+			/* USB and EHCI */
+			Package() { 0x001affff, 0, 0, 0x10 },
+			Package() { 0x001affff, 1, 0, 0x11 },
+			Package() { 0x001affff, 2, 0, 0x12 },
+			/* High Definition Audio	0:1b.0 */
+			Package() { 0x001bffff, 0, 0, 0x10 },
+			/* PCIe Root Ports		0:1c.x */
+			Package() { 0x001cffff, 0, 0, 0x10 },
+			Package() { 0x001cffff, 1, 0, 0x11 },
+			Package() { 0x001cffff, 2, 0, 0x12 },
+			Package() { 0x001cffff, 3, 0, 0x13 },
+			/* USB and EHCI			0:1d.x */
+			Package() { 0x001dffff, 0, 0, 0x10 },
+			Package() { 0x001dffff, 1, 0, 0x11 },
+			Package() { 0x001dffff, 2, 0, 0x12 },
+			Package() { 0x001dffff, 3, 0, 0x13 },
+			/* SMBUS/SATA/PATA	0:1f.2, 0:1f.3 */
+			Package() { 0x001fffff, 1, 0, 0x11 },
+		})
+	} Else {
+		Return (Package() {
+			/* PEG */
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* Internal GFX */
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* ME */
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+
+			Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			/* GBE */
+			Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* USB */
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			/* High Definition Audio	0:1b.0 */
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			/* PCIe Root Ports		0:1c.x */
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			/* USB and EHCI			0:1d.x */
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			/* PATA/SATA/SMBUS		0:1f.1-3 */
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}