diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/mainboard/intel/dg41wv | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
| -rw-r--r-- | src/mainboard/intel/dg41wv/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/dg41wv/romstage.c | 15 |
2 files changed, 3 insertions, 14 deletions
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 295fbc4f38..c00e998bcc 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -65,6 +65,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x00fc0a01" # HWM + device pci 1b.0 on # Audio subsystemid 0x8086 0x5756 end diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index a6969ad4d2..c0127b6c45 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -56,19 +56,6 @@ static void mb_lpc_setup(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); - /* Fixed IO decode ranges */ - pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); - /* LPC enable devices */ - pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN - | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN - | COMB_LPC_EN | COMA_LPC_EN); - /* IO decode range: HWM on 0xa00 */ - pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -77,7 +64,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |