diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2021-03-23 12:23:45 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-24 05:43:05 +0000 |
| commit | 25ef410423df812f626b77b695f151b6f221fa2e (patch) | |
| tree | b8172d0a48af9d38d9f60ac325542369befbfd64 /src/mainboard/intel/dg41wv | |
| parent | cbe266142efa5020f05230c9e59f73a8263f0670 (diff) | |
soc/mediatek/mt8192: Enlarge ROMSTAGE to 272K
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache
(CB:51620). To have more compact space usage, reduce BOOTBLOCK size from
64K to 60K (only 44K needed), and move starting address of DRAM blob
(DRAM_INIT_CODE) to 0x210000 (64K-aligned).
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=asurada
Cq-Depend: chrome-internal:3704751
Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Diffstat (limited to 'src/mainboard/intel/dg41wv')
0 files changed, 0 insertions, 0 deletions